Adjustable Test Pattern Results Latency in Digital Instruments

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Solution Overview

Problem

Digital test instruments with varying results latencies can 'break' working test programs due to increased latency, making it challenging to run existing test programs on newer instruments with different latency characteristics.

Innovation Solution

A digital test instrument with a synchronization unit that provides a no-result indication for a preset number of pattern cycles followed by pass/fail results, allowing the pattern controller to generate sequences of test patterns responsive to pass/fail results and emulating the latency of older instruments, thus ensuring compatibility with original test programs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the operating speed of digital test instruments is increased to achieve high-speed performance, then productivity is improved, but results latency increases causing existing test programs to fail

Engineering Contradiction:
Improvetest speedVSAvoidresults latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the results latency configurable and adjustable rather than fixed. The system allows dynamic modification of the latency parameter to match different test program requirements, enabling the same hardware to adapt between high-speed operation and legacy program compatibility modes

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the latency parameter from a fixed hardware characteristic to a configurable parameter. By allowing users to set and adjust the results latency value, the system can optimize performance for different test scenarios and maintain compatibility with test programs designed for different latency characteristics

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the results latency is reduced to maintain compatibility with existing test programs, then adaptability is improved, but high-speed performance is compromised

Engineering Contradiction:
Improveprogram compatibilityVSAvoidtest speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The system dynamically adjusts the results latency based on the specific test program being executed. By making latency configurable, the instrument can switch between different latency modes to match the requirements of various test programs, whether legacy or modern, without being constrained to a single fixed value

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent makes the test instrument universal by enabling it to handle both old and new test programs with different latency expectations. The configurable latency parameter allows the same hardware platform to serve multiple functions and support diverse test program requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If test programs are modified to accommodate new instrument latency, then device complexity is reduced, but development cost and time increase

Engineering Contradiction:
Improvetest program complexityVSAvoidprogram development time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

Instead of modifying test programs to match the instrument's fixed latency, the patent inverts the approach by allowing the instrument to adapt its latency to match the test program's requirements. This eliminates the need for costly and time-consuming program modifications

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentEP2212787B1Adjustable test pattern results latency
Publication Date: 2017.07.26 TERADYNE INC
  • EP2212787B1 patent drawingFigure 1A~1B
  • EP2212787B1 patent drawingFigure 2
  • EP2212787B1 patent drawingFigure 3

AI summary

A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.