Adjustable Threshold Voltage Transistors via Buried Trapping Zones
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Solution Overview
Problem
Current technologies fail to simultaneously produce optimized fully depleted (FD) transistors with adjustable threshold voltages suitable for both logic and analog applications, particularly for short channels, as existing methods face challenges in electrostatic control and variability.
Innovation Solution
The solution involves creating an electronic sub-assembly with a conductive zone under the semiconductor layer, featuring trapping zones with different depths and trap densities, utilizing nano-crystals and a stack of oxide layers for charge storage and coupling, allowing for quasi-continuous adjustment of threshold voltage through substrate and drain biasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to produce fully depleted transistors, then electrostatic control is improved, but threshold voltage adjustability is lost
Solution Approach 1:
The patent incorporates trapping zones during the initial fabrication process of the fully depleted transistor structure. These trapping zones are pre-positioned in the insulating layer beneath the semiconductor layer, allowing threshold voltage adjustment capability to be built into the device architecture from the start, rather than requiring post-fabrication modifications.
Solution Approach 2:
The patent introduces trapping zones as an intermediary mechanism between the insulating layer and the semiconductor channel. These trapping zones capture and hold charges that indirectly modulate the threshold voltage of the transistor, providing adaptability without disrupting the electrostatic control provided by the fully depleted structure.
2Adaptability or versatility
If threshold voltage is adjusted using floating-gate structures, then threshold voltage adjustability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the threshold voltage adjustment functionality from the complex floating-gate structure and implements it through simpler trapping zones formed directly in the insulating layer. This separates the electrostatic control function (handled by the fully depleted structure) from the threshold voltage adjustment function (handled by the trapping zones), reducing overall device complexity.
Solution Approach 2:
The trapping zones serve multiple functions: they provide threshold voltage adjustability, enable post-fabrication tuning, and maintain compatibility with standard fully depleted transistor fabrication processes. This multi-functionality eliminates the need for separate adjustment mechanisms, reducing device complexity.
3Adaptability or versatility
If threshold voltage is adjusted post-fabrication, then adaptability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent enables dynamic threshold voltage adjustment through controlled biasing of the trapping zones after fabrication. The trapping zones can be electrically programmed to capture or release charges, allowing the threshold voltage to be tuned dynamically based on circuit requirements without requiring precise physical modifications during manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables dynamic adjustment of threshold voltage for each transistor, optimizing performance based on application, compensating for technological fluctuations and environmental changes, and extending system lifetime by allowing reconfiguration of transistors post-fabrication.
Implementation Method 1
buried trapping layers
Implementation Method 2
capacitive coupling
Data Source
Figure 1~3
Figure 4~5
Figure 6~7
AI summary
The process comprises, for the realization of an electronic subassembly: - a step of assembling a semiconductor layer (103) carrying at least one first transistor (110) with adjustable threshold voltage and an insulating layer (102, 105) and - a step of forming in the insulating layer, at a first predetermined depth, a first trapping zone (220) extending at least under one channel of said first transistor and comprising traps with a density greater than the density of traps outside said first trapping zone such that the semiconductor layer and the first trapping zone are in capacitive coupling, the useful information of said first transistor being the transport of charges within this transistor.In some embodiments, a second trapping zone extending at least under one channel of a second transistor is formed by a second implantation with an energy and/or dose and/or atoms different from those used for the first trapping zone.