ADPLL Bandwidth Shifting Without Lock Loss
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Solution Overview
Problem
Switching loop bandwidth in all-digital phase locked loops (ADPLLs) often disturbs the lock, affecting ongoing communications, particularly in wireless communication devices.
Innovation Solution
Implementing a digital loop filter with flip-flops to store amplification parameters and using a dual-path structure to ensure continuity during bandwidth changes, allowing for seamless gear shifting without losing lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If loop bandwidth is switched to change loop gain for faster locking, then locking speed is improved, but the lock is disturbed and communication stability deteriorates
Solution Approach 1:
The patent implements dynamic loop bandwidth switching that adapts the loop bandwidth based on the locking state. During initial acquisition, a wider loop bandwidth is used to enable faster frequency and phase acquisition. Once locked, the loop bandwidth is narrowed to improve phase noise performance and maintain stable communication. This dynamic adjustment resolves the contradiction by optimizing the loop bandwidth for different operational phases without causing lock loss.
Solution Approach 2:
The patent changes the loop bandwidth parameter at different stages of the locking process. By transitioning from a wide bandwidth mode during acquisition to a narrow bandwidth mode during steady-state operation, the system achieves both fast locking and stable communication. The parameter change is controlled to avoid abrupt transitions that would disturb the lock.
2Loss of time
If loop bandwidth is increased for faster locking, then acquisition time is reduced, but phase noise outside channel bandwidth increases
Solution Approach 1:
The patent dynamically adjusts the loop bandwidth based on the locking state to resolve the trade-off between acquisition time and phase noise. During the acquisition phase, a wider loop bandwidth is employed to reduce acquisition time by allowing faster tracking of frequency and phase variations. Once the lock is achieved, the loop bandwidth is narrowed to filter out phase noise outside the channel bandwidth, thereby improving signal quality while maintaining the fast acquisition capability.
3Stability of the object's composition
If analog PLL is used with continuous bandwidth adjustment, then bandwidth changing is smooth, but switching speed is slower compared to digital solutions
Solution Approach 1:
The patent replaces the analog continuous bandwidth adjustment mechanism with a digital implementation. The digital loop filter uses digital signal processing to adjust the loop bandwidth, which enables faster switching speeds compared to analog circuits while maintaining smooth transitions through controlled parameter changes. The digital architecture allows for precise control of bandwidth transitions and can implement complex bandwidth switching strategies that would be difficult to realize in analog form.
Data Source
AI summary
This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.