ADPLL Phase Tracking with Dual-ADC Phase Comparison
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Solution Overview
Problem
Conventional all-digital phase locked loops (ADPLLs) employing time-to-digital converters (TDCs) suffer from poor integral non-linearity (INL) and differential non-linearity (DNL) performance, as well as high noise and power consumption, making them less ideal for phase detection.
Innovation Solution
Implementing a pair of analog-to-digital converters (ADCs) to sample the phase difference between an output signal and a reference signal in the ADPLL, which improves INL, DNL, and power consumption performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional time-to-digital converters (TDCs) are employed for phase detection in ADPLLs, then the device can perform phase detection, but the integral non-linearity (INL) and differential non-linearity (DNL) performance deteriorates
Solution Approach 1:
The patent replaces the conventional TDC (time-to-digital converter) mechanism with an ADC-based sampling system. Instead of using time-domain measurement which suffers from INL and DNL issues, the invention converts the phase detection to amplitude-domain sampling where the phase difference is transformed into voltage differences that can be accurately measured by ADCs, thereby eliminating the INL and DNL problems inherent in TDCs
Solution Approach 2:
The invention changes the measurement parameter from time domain (TDC approach) to voltage/amplitude domain (ADC approach). By converting the phase difference information into voltage signals through mixing and low-pass filtering, the system utilizes ADCs which have superior linearity characteristics, thus improving both INL and DNL performance while maintaining phase detection accuracy
2Measurement precision
If conventional time-to-digital converters (TDCs) are employed for phase detection in ADPLLs, then the device can perform phase detection, but the power consumption increases
Solution Approach 1:
The patent substitutes the power-hungry TDC circuitry with ADC-based sampling architecture. The new implementation uses mixers, low-pass filters, and ADCs which collectively consume less power than high-resolution TDCs, achieving the same phase detection function with improved power efficiency
3Measurement precision
If conventional time-to-digital converters (TDCs) are employed for phase detection in ADPLLs, then the device can perform phase detection, but the noise performance deteriorates
Solution Approach 1:
The invention replaces the TDC-based phase detection path with an ADC-based path that includes mixers and low-pass filters. This substitution eliminates the quantization noise and jitter issues inherent in TDCs, providing cleaner phase error signals with better noise performance
Solution Approach 2:
The patent introduces intermediate processing stages (mixers and low-pass filters) that act as mediators between the phase difference signal and the ADC. These intermediaries transform the phase information into frequency and voltage domains where noise can be filtered out, resulting in cleaner digital signals for the ADC to convert
Data Source
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AI summary
An ADPLL circuit includes a phase comparator for comparing a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCO_CLK) signal output from a DCO. The phase comparator includes a first ADC connected to receive a REF_P signal corresponding to the phase of the REFCLK signal via a first switch and output an ADC0 signal and a second ADC connected to receive the signal REF_P via a second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCO_CLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control a frequency of operation of the DCO based on the phase difference.