ADPLL Auto-Frequency Calibration for Fast Locking and Low Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase locked loop (PLL) designs exhibit slow locking times and high power consumption or increased chip size, particularly in wide-range digital logic quadricorrelator (WDLQ) based systems and counter-based systems, which are not suitable for fast synchronization in modern high-frequency applications.
Innovation Solution
An all-digital PLL (ADPLL) with an auto-frequency calibration mechanism, including a phase difference detector, code generator, digital loop filter, voltage-controlled oscillator, divider, and delta-sigma modulator, which uses a time-to-digital converter and a look-up table to determine the sampling period and generate coarse and fine tuning signals for efficient synchronization, reducing power consumption and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If WDLQ based systems are used for PLL synchronization, then synchronization capability is achieved, but locking time becomes slow
Solution Approach 1:
The patent segments the frequency adjustment process into two distinct phases: coarse tuning for rapid frequency acquisition and fine tuning for precise frequency matching. The code generator produces coarse tuning signals for fast locking, while the digital loop filter provides fine tuning for accuracy. This segmentation allows the system to achieve both fast locking time and reliable synchronization without the slow processing time inherent in WDLQ-based systems.
2Loss of time
If counter based system is used to achieve faster locking time, then locking time improves, but power consumption and chip size increase
Solution Approach 1:
The patent replaces the mechanical counter-based frequency measurement system with an all-digital approach using a time-to-digital converter (TDC) and code generator. The TDC measures time intervals digitally, and the code generator translates these measurements into tuning signals. This substitution eliminates the need for high-frequency clocks and large counters, achieving fast locking time while significantly reducing power consumption and chip size.
3Loss of time
If high frequency clock and counter are included in PLL, then locking time becomes faster, but chip size increases
Solution Approach 1:
The patent extracts and removes the high-frequency clock and large counter components from the PLL system. Instead, it implements a time-to-digital converter that operates at lower frequencies but achieves the same fast locking performance through precise time measurement and digital code generation. This extraction eliminates the chip area requirements for high-frequency clock circuits and large counter structures while maintaining fast locking capability.
Data Source
AI summary
A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.