ADPLL Power-Saving Mode Using Low-Frequency TDC Tracking

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Solution Overview

Problem

Existing all-digital phase locked loops (ADPLLs) face significant power consumption issues due to the high power intensity of the time-to-digital converter (TDC), which affects the efficiency of wireless communication systems.

Innovation Solution

The ADPLL is designed with a dual-mode operation, switching between normal and power saving modes, where the TDC operates with low-frequency signals after lock is achieved, reducing dynamic activity and power consumption by using a CKV snapshot signal and a fixed TDC gain for fractional phase error calculation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the TDC operates with high-frequency signals to maintain precise phase tracking, then measurement precision is improved, but power consumption increases

Engineering Contradiction:

Improvephase tracking precisionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The TDC operates dynamically in two modes: during lock acquisition it processes high-frequency DCO output signals for precise phase measurement, and during normal operation it switches to low-frequency CKV snapshot signals to reduce power consumption while maintaining adequate tracking precision through fixed gain calculation

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the operating parameters of the TDC by switching between different input signal frequencies (high-frequency DCO output during acquisition vs. low-frequency CKV snapshot during normal operation) and adjusts the gain calculation method (dynamic vs. fixed) to optimize the trade-off between measurement precision and power consumption

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If the TDC processes high-frequency DCO output signals continuously, then phase error detection accuracy is improved, but dynamic activity and power consumption increase

Engineering Contradiction:

Improvephase error detection accuracyVSAvoiddynamic activity power

Core Design Contradiction:

Measurement precisionVSLoss of energy

Solution Approach 1:

Instead of continuous high-frequency processing, the system uses periodic CKV snapshot signals at lower frequency to capture phase information. The snapshot approach periodically samples the phase relationship between reference and VCO signals, reducing the continuous dynamic activity in the TDC while maintaining sufficient measurement accuracy for locked operation

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS20260031822A1All-digital phase locked loop with power saving mode for wireless communication devices

Publication Date: 2026.01.29 MORSE MICRO PTY LTD

AI summary

Wireless communication devices have an all-digital phase locked loop (ADPLL) including a digital controlled oscillator, a counter, a time to digital converter, a phase detector, and a digital loop filter. The digital controlled oscillator (DCO) generates a DCO output signal (CKV) to synchronize with a reference clock signal (FREF), and the counter generates an integer part from CKV. The time to digital converter detects a time difference between a reduced frequency signal and FREF, where this reduced frequency signal is generated from CKV. The phase detector estimates a fractional part based on the time difference and derives a phase error based on the integer part from the counter, the fractional part, and a goal frequency. The digital loop filter receives the phase error and provides tracking codes to the DCO to adjust the frequency of its output signal.