ADPLL PWM-Based DCO Resolution Enhancement for Low Phase Noise
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Solution Overview
Problem
All digital phase-locked loops (ADPLLs) face performance issues due to time-to-digital conversion (TDC) and digital controlled oscillator (DCO) quantization errors, which contribute to phase noise, and require carefully matched custom designs for improved resolution using digital-to-analog converters (DACs) and delta-sigma modulators (DSMs).
Innovation Solution
The implementation of a PWM-based resolution enhancement technique in ADPLLs, which uses tunable delay elements and a pulse-width modulation (PWM) circuit to control the DCO, eliminating the need for DACs and DSMs, and allowing for adaptive digital loop filtering to suppress noise and enhance resolution to 59 kHz steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional DAC and DSM are used to improve DCO resolution, then DCO resolution is improved, but device complexity and manufacturing difficulty increase due to carefully matched custom design requirements
Solution Approach 1:
The patent extracts and eliminates the DAC and DSM components from the ADPLL system by replacing them with a PWM-based resolution enhancement technique. This removes the need for carefully matched custom design of these complex components while maintaining improved DCO resolution through digital domain processing.
Solution Approach 2:
The patent substitutes the analog/mixed-signal DAC and DSM mechanisms with a purely digital PWM-based approach. The resolution enhancement is achieved through digital signal processing and delay element control rather than through analog conversion components, simplifying the overall design.
2Object-affected harmful factors
If TDC and DCO quantization errors are reduced through complex matching, then phase noise performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a self-correcting mechanism where the PWM-based resolution enhancement technique automatically compensates for TDC and DCO quantization errors through digital feedback processing. The system uses the phase error information to dynamically adjust the PWM duty cycle, thereby reducing phase noise without requiring high-precision component matching.
Solution Approach 2:
The patent changes the operating parameters of the DCO by using PWM modulation to control the delay elements. This allows dynamic adjustment of the DCO frequency and phase with fine resolution, reducing quantization errors and phase noise through parameter optimization rather than through precise component manufacturing.
3Measurement precision
If custom matched design is used to improve resolution, then DCO resolution improves, but ease of manufacture deteriorates
Solution Approach 1:
The patent creates a universal ADPLL design that can be manufactured across different processes and technologies. The PWM-based resolution enhancement technique is process-independent and can be implemented using standard digital logic cells, making the design portable and easy to manufacture without requiring custom matched components for each process node.
Data Source
AI summary
An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (fREF) at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to multiple tunable delay elements; receiving at the multiple tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output (fDCO) to the TDC at least partially based on the first signal input; and generating a phase error output (ΦERR) based on the reference signal (fREF) and the PLL output (fDCO), wherein the phase error output (ΦERR) is provided as feedback to the controller to control the PLL output (fDCO).