ADPLL Voltage Doubler Control for Stable TDC Resolution
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Solution Overview
Problem
All-digital phase locked loops (ADPLLs) face fluctuations in time-to-digital converter (TDC) resolution due to process, voltage, and temperature (PVT) variations, leading to varying in-band phase noise.
Innovation Solution
Incorporating voltage doubler circuitry to scale the analog input supply voltage and digital circuitry to regulate the digital input supply voltage, stabilizing the TDC resolution across PVT variations through calibration and switching clocking signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage scaling is performed using conventional voltage regulators, then the digital input supply voltage can be provided, but the TDC resolution fluctuates due to PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the TDC measures phase differences between clock signals, and this measurement is used to control a voltage doubler circuit that adjusts the digital supply voltage. The phase error signal from the TDC feeds back to the voltage doubler, creating a closed-loop system that automatically compensates for voltage variations and stabilizes the TDC resolution across PVT conditions.
Solution Approach 2:
The patent changes the operating parameters of the voltage scaling circuit by using a voltage doubler circuit instead of a conventional regulator. The voltage doubler dynamically adjusts its output voltage based on the phase error signal, changing the voltage parameter in response to PVT variations to maintain stable TDC resolution. This involves switching between different voltage levels to compensate for process, voltage, and temperature effects.
2Object-generated harmful factors
If the digital input supply voltage is regulated to stabilize TDC resolution, then in-band phase noise is reduced, but the device complexity increases
Solution Approach 1:
The voltage doubler circuit serves multiple functions: it scales the analog input voltage to the required digital voltage level, and simultaneously acts as a variable voltage regulator controlled by the TDC feedback. This multi-functionality eliminates the need for separate voltage regulation circuitry, reducing overall device complexity while achieving phase noise reduction through stabilized TDC operation.
Solution Approach 2:
The system uses its own internal phase error signal to automatically regulate the supply voltage without requiring external control. The TDC's phase measurement directly controls the voltage doubler, creating a self-regulating system that reduces phase noise while minimizing the need for additional control circuitry or external components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Maintains a fixed in-band phase noise across PVT variations by stabilizing the TDC resolution, ensuring consistent ADPLL performance.
Implementation Method 1
the voltage doubler circuitry charges or discharges one or more switchable capacitors in accordance with a switching clocking signal to provide the supply voltage
Data Source
AI summary
An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.