Advanced Initialization Bus With Slave-Clock Data Latching
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Solution Overview
Problem
Conventional multi-chip module (MCM) communication buses, such as QSPI, face limitations in frequency and distance due to timing discrepancies between master and slave dies, leading to setup time issues and incorrect data latching.
Innovation Solution
The advanced initialization bus (AIB) employs a serial clock and a control/clock signal to synchronize data strobes, allowing the AIB slave to provide a synchronized data latching signal to the AIB master, using an asynchronous first-in, first-out buffer for data capture, thereby maintaining data setup and hold requirements at higher frequencies and longer distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional QSPI bus is used for communication between master and slave dies, then the communication can be established, but timing discrepancies occur between master and slave dies leading to setup time issues and incorrect data latching
Solution Approach 1:
The slave die's internal clock is used as an intermediary signal to synchronize data latching at the master die. Instead of relying on the master's clock which causes timing discrepancies, the slave's clock is transmitted back to the master to serve as the latching reference, eliminating setup time issues caused by clock skew.
Solution Approach 2:
Conventionally, the master die's clock is used to latch slave data. This invention inverts the approach by using the slave die's clock (transmitted via the CC signal line) to latch data at the master die, thereby resolving the timing discrepancy problem inherent in traditional master-clock-based synchronization.
2Productivity
If higher frequencies are used for communication, then communication efficiency improves, but timing discrepancies and setup time issues worsen
Solution Approach 1:
The slave die's clock signal is fed back to the master die through the control/clock (CC) signal line. This feedback mechanism ensures that the master die uses the exact same clock timing reference that the slave die uses for data output, maintaining reliable data capture even at higher frequencies where timing margins are reduced.
3Adaptability or versatility
If longer distances are used between dies, then device integration flexibility improves, but signal timing synchronization deteriorates
Solution Approach 1:
The slave clock signal acts as an intermediary that travels along with the data signals over the same physical distance. Since both data and clock experience identical propagation delays over long traces, using the slave clock for latching at the master die maintains timing synchronization regardless of the physical distance between dies.
Data Source
AI summary
Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.