Electric Digital Data Processing TRIZ Cases
- Fabric Connection Transceiver Identification via Wireless EEPROM
A wireless EEPROM lets mobile technicians verify transceiver identity before fabric connection, reducing selection and configuration errors.
- D-Bus Object Proxy Caching for BMC Performance
Repeated BMC requests for D-Bus objects slow retrieval; a proxy cache serves stored data while preserving manageability and customization.
- Programmable DPU Ingress Bypass for Lower-Latency RDMA Packets
Packet header matching routes RDMA packets to DMA pipelines, avoiding unnecessary networking stages and reducing DPU latency.
- Information Processing Apparatus for Enabled Connection Selection
The apparatus detects enabled connection methods before selection, reducing user confusion and improving setup reliability.
- PCIe Link Lane Reconfiguration for Faster NACK Retransmission
When NACK-flagged FLITs block the replay buffer, PCIe widens the link for faster retransmission before restoring normal lane use.
- Crossbar Transpose Memory for Parallel Matrix Data Transfers
Diagonal storage and row rotation let a crossbar write transposed arrays in parallel, reducing memory latency and DMA overhead.
- UART Spill Buffer and DMA Recovery for High Baud Rates
A spill buffer captures UART data during DMA setup, while recovery routines preserve reliability at higher baud rates.
- Auxiliary Bus Master Circuit Preventing Burst Transfer Interruptions
Low-priority transfers can interrupt high-priority bus bursts; an auxiliary master times access requests to keep critical transfers moving.
- Storage Queue Switching for Continuous I/O During OS Updates
Halting a CPU for an SMP OS update can interrupt host I/O; queue switching reroutes commands to an active controller CPU for continuity.
- D-Sub Connector I2C Monitoring for Server Diagnostics
Repurposed D-sub pins carry I2C signals to an I/O expander that drives LEDs for real-time server diagnostics.
- PCIe Switch Architecture for Multi-Host SR-IOV Device Sharing
Multiple PCIe hosts access SR-IOV virtual functions through emulated PCIe devices and hardware transaction bridging without specialized host software.
- Low-Latency Command Propagation for Automotive LEDs and Sensors
A single-initiator UTP network uses branch devices and mode switching to control vehicle LEDs and sensors with fail-safe, low-latency behavior.
- Programmable Data Plane LPM With Distributed Interval Trees
A modified binary search on interval trees enables programmable IO devices to classify packets for scalable LPM with lower CPU load.
- Hybrid Cloud Recovery Replication with Parallel Shadow Volumes
Parallel I/O-group mirroring uses shadow and emulated volumes to reduce latency and free cache space sooner during hybrid-cloud recovery.
- Auxiliary Bus Master Circuit for Uninterrupted Priority Transfers
Timed access requests help an auxiliary bus master prevent lower-priority interruptions and complete high-priority transfers quickly.
- APB Serial Communication Device With Autonomous Shift Registers
An intermediary shift-register path transfers write and read data between APB master and slave interfaces, reducing frequent interrupts and master resource consumption.
- Burst-Aware SSD Host Scheduler for PCIe Transaction Efficiency
PCIe arbitration can waste bus capacity through packet overhead; burst-aware SSD scheduling groups transactions for better host DRAM use.
- Semiconductor Device Bus Arbitration for DR Processor DMA Access
A bus arbiter and denial-frequency circuit prioritize processor and DMA memory access to reduce waits during AI and image processing.
- Storage Controller Path Switching for Host-Continuous Replacement
Preconfigured dual controllers and switch-managed paths replace a storage controller without host downtime or I/O data loss.
- I2C Dynamic Address Assignment for Conflict-Free Slave Identification
ACK feedback and random slave delays let an I2C master assign unique addresses, avoiding conflicts without extra signals or multiplexers.
- Dynamic Signal Correction for I/O Card Link-Up Reliability
Device identification triggers dynamic correction-parameter updates, helping new I/O cards avoid signal distortion and link-up failures.
- Advanced Initialization Bus With Slave-Clock Data Latching
Slave-provided clock feedback lets the AIB latch read data reliably across longer die-to-die links and higher frequencies.
- AFIFO Grouping in Interconnection Circuitry for Variable Bus Widths
Grouping AFIFOs across interfaces supports different data bus widths while reducing circuit area and manufacturing cost.
- DMA Read Reassembly Circuit Using Shared Buffer Allocation
Duplicated reorder buffers consume resources and throttle bandwidth; a centralized circuit reorders completions across DMA read channels.
- Sensor Frame-Sync DMA for Lower Processor Load
A DMA engine detects synchronized sensor frames, discards invalid data, and sends extracted payloads to memory with less processor work.
- Full-Duplex SPI Driver With IRQ-Ready Payload Synchronization
An SPI peripheral repurposes its IRQ line as a READY signal, preventing payload loss without fixed delays and enabling full-duplex transfer.
- HID Virtual Endpoint Segmentation for Lower Polling Latency
Multiple virtual endpoints and dummy packets keep HID polling active between sensor updates, reducing latency without faster communication channels.
- Active Silicon Bridge Chiplets for Scalable XPU-Memory Integration
Active silicon bridge chiplets connect processor dies with stacked memory, scaling XPU integration beyond lithography limits.
- Computer Peripheral USB Bridge for High-Speed HID Signals
A USB bridging device lets a low-speed HID use high-speed host communication without changing the HID control unit.