Auxiliary Bus Master Circuit for Uninterrupted Priority Transfers
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Solution Overview
Problem
Existing data transfer systems fail to ensure continuous high-priority data transfer by a specific bus master is completed in a short time due to interruptions from lower-priority bus masters, even with maximum priority setting.
Innovation Solution
An auxiliary bus master circuit that includes a control circuit to manage access requests based on high-priority master signals, ensuring continuous data transfer by prioritizing and completing high-priority transfers quickly, while preventing lower-priority interruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high priority degree master circuit issues continuous transfer requests (single transfer or burst transfer), then data transfer priority is maintained, but lower priority master circuits can still interrupt between transfer requests, causing transfer delays
Solution Approach 1:
The patent introduces an auxiliary bus master circuit as an intermediary between the high priority master circuit and the bus arbitration system. This auxiliary master continuously issues dummy transfer requests to occupy the bus, preventing lower priority masters from interrupting the high priority master's data transfer operations, thereby ensuring continuous transfer completion without interruptions
2Adaptability or versatility
If a bus arbitration system allows multiple masters to share the bus, then system versatility is improved, but high priority master circuits cannot guarantee continuous transfer due to interruptions from other masters
Solution Approach 1:
The auxiliary bus master acts as a protective intermediary that monitors the bus state and continuously issues dummy requests when the high priority master is actively transferring data. This mechanism preserves the multi-master system architecture while creating a protected transfer window that guarantees uninterrupted high-speed data transfer for priority masters
Data Source
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AI summary
An auxiliary bus master circuit (100) is connected or connectable to a bus (400) in a system (500) in which a high priority degree master circuit (200) having a bus access right having a high degree of priority and a low priority degree master circuit (300) having a bus access right having a lower degree of priority than the high priority degree master circuit (200) are connected to one bus (400), and the auxiliary bus master circuit (100) includes a control circuit (110) that outputs an access request signal for requesting an access right from the bus (400), based on a timing for outputting at least one of high priority degree master signals being signals exchanged by the high priority degree master circuit (200) through the bus (400).