UART Spill Buffer and DMA Recovery for High Baud Rates

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Solution Overview

Problem

The UART protocol is susceptible to data loss due to the peripheral device's limited resources and inability to configure the DMA controller before the host begins transmitting the payload, especially at higher baud rates, leading to reduced throughput and increased data loss.

Innovation Solution

Implementing a spill buffer and recovery routine on the peripheral device to capture and process data before the DMA controller is configured, using buffer descriptors and interrupt service routines to manage data transmission and recovery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the peripheral device uses a low baud rate to configure the DMA controller, then the configuration time is sufficient, but the data throughput is reduced

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiddata throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The peripheral device pre-configures the DMA controller with buffer descriptors before receiving data. The spill buffer captures headers and payloads that arrive during the configuration period, allowing the DMA controller to be pre-prepared for immediate data reception without waiting for the host to slow down its transmission rate.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spill buffer acts as an intermediary between the host and the DMA controller. It temporarily stores data (headers and payloads) that arrive before the DMA controller is fully configured, bridging the timing gap between data transmission and DMA setup, thereby enabling higher baud rates without data loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the peripheral device increases the baud rate to improve throughput, then data transmission speed increases, but data loss increases due to insufficient time to configure the DMA controller

Engineering Contradiction:
Improvedata throughputVSAvoiddata transmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The peripheral device pre-configures the DMA controller with buffer descriptors before receiving data. The spill buffer captures headers and payloads that arrive during the configuration period, allowing the DMA controller to be pre-prepared for immediate data reception without waiting for the host to slow down its transmission rate.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spill buffer acts as an intermediary between the host and the DMA controller. It temporarily stores data (headers and payloads) that arrive before the DMA controller is fully configured, bridging the timing gap between data transmission and DMA setup, thereby enabling higher baud rates without data loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the peripheral device uses a single processor to service tasks, then the device complexity is reduced, but data loss occurs when the processor is servicing higher priority tasks

Engineering Contradiction:
Improveprocessor configurationVSAvoiddata reception reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The peripheral device pre-configures the DMA controller with buffer descriptors before receiving data. The spill buffer captures headers and payloads that arrive during the configuration period, allowing the DMA controller to be pre-prepared for immediate data reception without waiting for the host to slow down its transmission rate.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spill buffer acts as an intermediary between the host and the DMA controller. It temporarily stores data (headers and payloads) that arrive before the DMA controller is fully configured, bridging the timing gap between data transmission and DMA setup, thereby enabling higher baud rates without data loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12423254B2Interrupt latency resilient UART driver
Publication Date: 2025.09.23 SILICON LABORATORIES INC
  • US12423254B2 patent drawing
  • US12423254B2 patent drawing
  • US12423254B2 patent drawing

AI summary

A system and method of reducing data loss in a system utilizing a bus protocol that does not support flow control is disclosed. The peripheral device utilizes a spill buffer which is used to capture any data sent by the host before the peripheral device is able to properly configure the DMA controller. Additionally, the peripheral device includes a recovery routine, which is a software program that parses the spill buffer and extracts any headers or payloads that are contained therein. Using the spill buffer and recovery routine, the baud rate of the bus interface may be increases without incurring any increase in data loss.