Sensor Frame-Sync DMA for Lower Processor Load
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Solution Overview
Problem
Existing DMA systems cause a high baseload on computing systems when processing sensor data due to the need for validation and extraction of payload from sensor data, leading to inefficient data processing.
Innovation Solution
A DMA system that includes input interface circuitry to receive data packets, processing circuitry to identify synchronized data frames, and output interface circuitry to extract and send payloads to destination memory, offloading processor tasks such as validation and preprocessing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the computing system configures a DMA engine to move entire sensor data from receive buffer to internal memory, then data transfer is achieved, but the processor experiences high baseload due to validation and payload extraction requirements
Solution Approach 1:
The patent extracts the payload extraction and validation functions from the processor and implements them within the DMA engine itself. The DMA engine now includes processing circuitry that can identify synchronized data frames and extract payloads directly during the data transfer process, eliminating the need for the processor to handle these tasks separately and thereby reducing processor baseload.
Solution Approach 2:
The patent merges the data transfer function with the payload extraction and validation functions into a single integrated DMA engine operation. By combining these previously separate operations into one unified process that occurs during data transfer, the system eliminates the need for the processor to sequentially perform validation, extraction, and transfer operations, thus reducing processor load while maintaining data transfer efficiency.
2Reliability
If the computing system performs validation and payload extraction after data transfer, then data processing is completed, but the overall processing time increases due to sequential operations
Solution Approach 1:
The patent performs validation and payload extraction actions during the data transfer process itself, rather than sequentially after transfer. The DMA engine's processing circuitry validates data frames and extracts payloads in parallel with the data movement operation, completing these tasks preliminarily before the transfer finishes. This preliminary action eliminates sequential processing delays and reduces overall processing time while ensuring data processing completeness.
Solution Approach 2:
The patent ensures continuous useful action by performing validation and payload extraction operations concurrently with data transfer operations. Instead of completing transfer first then performing validation and extraction, the system maintains continuous productive activity where the DMA engine simultaneously executes transfer, validation, and extraction functions, eliminating idle time and reducing total processing duration while maintaining complete data processing.
3Ease of manufacture
If the DMA engine processes entire sensor data packets, then data transfer is simplified, but the system cannot efficiently handle unsynchronized or invalid data frames
Solution Approach 1:
The patent applies local quality by enabling the DMA engine to selectively process only the relevant portions of data packets - specifically identifying and extracting payloads from synchronized data frames while skipping or discarding unsynchronized or invalid frames. The processing circuitry within the DMA engine examines individual frame characteristics and applies appropriate processing only where needed, maintaining data transfer simplicity while improving synchronization accuracy through localized quality control.
Data Source
AI summary
In accordance with an embodiment, a direct memory access (DMA) system includes input interface circuitry configured to receive a data packet of a sensor from a source memory. The DMA system comprises processing circuitry configured to determine whether the data packet comprises a synchronized data frame and, when it is determined that the data packet comprises a synchronized data frame, extract a payload of the synchronized data frame. The DMA system comprises output interface circuitry configured to send the payload or data derived from the payload to a destination memory.