Semiconductor Device Bus Arbitration for DR Processor DMA Access
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Solution Overview
Problem
The insufficient bandwidth of the common bus in semiconductor devices with a dynamically reconfigurable processor (DR processor) leads to memory access waits, reducing the performance and making it difficult to continuously display images at 30 frames per second during AI inference and image processing.
Innovation Solution
A semiconductor device with a processor, DR processor, and image processing circuit connected to a common bus, utilizing a bus arbiter for arbitration and a DMA controller, along with a frequency circuit to determine memory access frequency, allowing prioritized access and reducing performance reduction by selecting appropriate state information based on denial frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bandwidth of the common bus is increased to enable high-speed memory access for AI processing and image processing, then the processing speed is improved, but the device complexity increases
Solution Approach 1:
The bus arbiter dynamically adjusts priority levels for different bus masters (processor, DR processor, image processing circuit) based on real-time access requirements. The priority order is not fixed but can be changed adaptively to match the current processing needs, allowing the system to optimize memory access speed without permanently increasing bus complexity
Solution Approach 2:
The system changes the parameter of bus access priority dynamically. By modifying the priority order parameter in response to different processing scenarios (AI inference vs. image display), the system achieves high memory access speed when needed while maintaining a manageable bus architecture that doesn't require permanent high-bandwidth upgrades
2Productivity
If the bandwidth of the common bus is increased to prevent memory access waits during AI inference and image processing, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The bus arbiter implements dynamic priority adjustment based on the current operational state. When AI inference is the primary task, the DR processor receives higher priority; when image display is critical, the image processing circuit gets priority. This dynamic approach maintains high productivity without requiring a permanently high-bandwidth complex bus system
Solution Approach 2:
The bus arbiter automatically manages memory access arbitration based on pre-set priority rules and real-time conditions, without requiring external intervention or complex control logic. The system self-regulates the memory access flow to maintain high productivity while keeping the bus architecture relatively simple
3Reliability
If memory access arbitration is implemented with priority ordering between processor and DMA controller, then the reliability of memory access is improved, but the device complexity increases
Solution Approach 1:
The bus arbiter uses a simple priority order parameter that can be configured but doesn't require complex real-time calculations. The priority levels are set based on the type of bus master and current operational mode, providing reliable memory access through a relatively simple arbitration mechanism rather than complex dynamic scheduling algorithms
Data Source
AI summary
A semiconductor device capable of suppressing reduction in performance is provided. The semiconductor device includes: a processor; a DR processor including a DMA controller; a system memory; an internal bus to which the processor, the DR processor, and the system memory are connected; and a bus arbiter connected to the processor and the DR processor, the bus arbiter executing arbitration between access to the system memory by the processor and access to the system memory by the DMA controller in accordance with a predetermined priority order. Here, the DR processor includes a frequency circuit determining a frequency at which the access to the system memory by the DMA controller is not permitted by the arbitration made by the bus arbiter.