AFIFO Grouping in Interconnection Circuitry for Variable Bus Widths
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Solution Overview
Problem
Conventional accelerator devices require a large number of asynchronous first-in-first-out shift registers (AFIFOs) to accommodate different data bus widths, leading to increased circuit area and manufacturing costs due to the need for dedicated AFIFOs for each interface, which limits the efficiency of data transfer and pin sharing.
Innovation Solution
Grouping multiple AFIFOs together based on data bus widths and regrouping them to accommodate different data bus widths, reducing the total number of AFIFOs needed and minimizing circuit area while maintaining performance and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated AFIFOs are provided for each interface to accommodate different data bus widths, then data transfer capability is improved, but circuit area and manufacturing cost increase
Solution Approach 1:
The patent implements multi-functionality by enabling AFIFOs to serve multiple interfaces with different data bus widths through configurable interconnection circuitry. The same AFIFO resource can be dynamically assigned to different interfaces based on their data width requirements, eliminating the need for dedicated AFIFOs for each interface while maintaining full data transfer capability across all interfaces
Solution Approach 2:
The patent applies dynamics by introducing configurable interconnection circuitry that can dynamically reconfigure the connection between AFIFOs and interfaces based on the data bus width requirements. This dynamic reconfiguration allows the system to adapt to different data transfer scenarios without requiring static dedicated AFIFO assignments, thereby reducing circuit area while preserving productivity
2Productivity
If dedicated AFIFOs are provided for each interface, then data transfer performance is maintained, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by implementing a universal AFIFO allocation mechanism where a single pool of AFIFOs can be dynamically assigned to multiple interfaces with different data bus widths. This eliminates the need for separate dedicated AFIFO blocks for each interface, simplifying the overall device architecture while maintaining data transfer performance through proper resource allocation and interconnection configuration
3Area of stationary object
If multiple AFIFOs are grouped and regrouped to accommodate different data bus widths, then circuit area is reduced, but configuration complexity increases
Solution Approach 1:
The patent manages configuration complexity through dynamic reconfiguration mechanisms. The configurable interconnection circuitry automatically determines the optimal grouping and regroupping of AFIFOs based on the data bus width requirements of connected interfaces. This dynamic approach eliminates manual configuration complexity by having the system self-configure according to operational needs, thereby reducing circuit area without proportionally increasing configuration complexity
Data Source
AI summary
An interconnection circuitry of an accelerator device includes a multiplexer, a first plurality of buffers, a second plurality of buffers, and a demultiplexer. The multiplexer is coupled to first offload circuitry and received data therefrom. The first plurality of buffers has inputs coupled to outputs of the multiplexer. A second plurality of buffers has inputs coupled to outputs of the first plurality of buffers. The demultiplexer includes inputs coupled to outputs of the second plurality of buffers and outputs coupled to inputs of programmable logic.