DMA Read Reassembly Circuit Using Shared Buffer Allocation
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Solution Overview
Problem
Existing DMA systems in peripheral devices require duplicating reorder buffers and reorder logic across read circuits, leading to increased resource consumption and limited flexible multi-channel operation, with bandwidth throttling due to latency in slowest read requests.
Innovation Solution
Implement a centralized read reassembly circuit (RRC) shared among multiple read circuits, using a read scheduler and linked list subsystems to reorder and manage data memory entries dynamically, allowing non-blocking DMA processes and efficient data availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reorder buffers and reorder logic are duplicated across each read circuit, then each read circuit can independently reassemble data, but resource consumption and device complexity increase
Solution Approach 1:
The patent merges the reorder buffer and reorder logic into a single shared resource that is common to all read circuits, eliminating the need for duplication. This shared reorder buffer is accessed by multiple read circuits through a unified structure, reducing overall resource consumption while maintaining the data reassembly capability for each read circuit.
Solution Approach 2:
The shared reorder buffer serves multiple read circuits simultaneously, making it a universal resource. Each read circuit can utilize the same reorder buffer for its data reassembly operations, allowing one resource to perform multiple functions across different read circuits rather than requiring separate dedicated buffers for each.
2Reliability
If reorder buffers and reorder logic are duplicated across each read circuit, then data reassembly is supported, but flexible multi-channel operation is limited
Solution Approach 1:
By merging the reorder buffers into a single shared structure, the system enables more read circuits to operate simultaneously with flexible multi-channel capabilities. The shared buffer can be dynamically allocated and accessed by different read circuits depending on their operational needs, enhancing adaptability rather than limiting it.
Solution Approach 2:
The shared reorder buffer implementation allows dynamic allocation and access patterns where read circuits can be assigned buffer resources based on their operational requirements. This dynamic sharing enables flexible multi-channel operation as the system can adaptively manage buffer access among multiple concurrent read circuits.
3Reliability
If each read circuit has its own reorder buffer, then data reassembly is independent, but bandwidth is throttled by the slowest read request
Solution Approach 1:
The shared reorder buffer allows multiple read circuits to operate in parallel without being constrained by individual buffer latencies. Since the buffer is shared rather than duplicated, the system can better manage data flow and reduce the impact of slowest read requests on overall bandwidth performance.
Solution Approach 2:
The shared reorder buffer acts as an intermediary resource that mediates between multiple read circuits and the data source. This intermediary structure allows for more efficient data flow management and can prevent bandwidth throttling by smoothing out the impact of individual slow read requests across the entire system.
Data Source
AI summary
A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and submit the read requests to the one more data processing systems via the switch. The DMA system includes a read reassembly circuit coupled to the plurality of read circuits, the switch, and the read scheduler circuit. The read reassembly circuit is configured to reorder read completion data received from the switch for the read requests and provide read completion data, as reordered, to the plurality of read circuits.