Programmable DPU Ingress Bypass for Lower-Latency RDMA Packets

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Solution Overview

Problem

Existing DPUs process packets through both networking and DMA pipelines, leading to increased latency for packets with minimal network-heavy tasks, such as RDMA over Converged Ethernet (ROCE) packets.

Innovation Solution

A DPU with a parser circuit to identify packet header vectors (PHVs) and match circuitry to determine if packets can bypass the networking pipeline, editing the PHV to direct them directly to the DMA pipeline, thereby reducing unnecessary processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If packets are processed through both networking and DMA pipelines, then comprehensive network processing is achieved, but latency increases for packets with minimal network-heavy tasks

Engineering Contradiction:

Improvepacket latencyVSAvoidpipeline processing complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The packet processing system is segmented into two distinct pipeline types: networking pipelines for complex network tasks and DMA pipelines for direct memory access. The match circuitry segments the packet flow by identifying which packets should bypass the networking pipeline and be directed directly to DMA pipelines, thereby reducing latency for packets that don't require extensive network processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different processing paths are applied to different packets based on their specific requirements. Latency-sensitive packets (such as RDMA packets) are routed through the optimized DMA pipeline path, while other packets continue through the full networking pipeline. This local quality approach ensures that each packet receives the appropriate level of processing based on its needs.

Inventive Principle:

Principle #3Local quality

2Productivity

If all packets are routed through the networking pipeline, then network protocol compliance is ensured, but compute resources are wasted on latency-sensitive packets

Engineering Contradiction:

Improvecompute resource utilizationVSAvoidnetwork processing reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The match circuitry extracts latency-sensitive packets from the general packet flow by examining packet headers and identifying specific packet types (such as RDMA packets). These extracted packets are then directed to the optimized DMA pipeline path, removing them from the standard networking pipeline processing to conserve compute resources while maintaining reliability for packets that require full network processing.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The system dynamically routes packets based on real-time packet analysis. The match circuitry continuously evaluates incoming packets and dynamically directs them to appropriate pipelines (networking or DMA) based on packet type and processing requirements, optimizing resource utilization while maintaining processing reliability.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12423255B1Programmable traffic ingress direction for reduced latency in a DPU

Publication Date: 2025.09.23 ADVANCED MICRO DEVICES INC

AI summary

Embodiments herein describe selectively bypassing a networking pipeline in a DPU. For example, instead of a packet being processed by both the networking pipeline and a DMA pipeline in the DPU, the packet is only processed by the DMA pipeline. This can reduce latency for packets that do not have network-heavy tasks associated with them, such Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE) packets. In addition, the DPU can perform load balancing between different instances of the pipelines in the DPU.