Storage Queue Switching for Continuous I/O During OS Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In storage systems with a one-to-one connection between a protocol chip and a controller, performing a non-disruptive OS update on a multicore CPU in an SMP OS is challenging, as it requires halting all cores, leading to loss of I/O control and potential disruption of communication with the host server.
Innovation Solution
The solution involves switching the queue used for I/O control on the controller side from a queue assigned to a halted CPU to a queue assigned to another controller CPU that is not halted, using PCI switches to reroute communication paths between protocol chips and CPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a one-to-one connection between protocol chip and controller is used, then communication reliability is improved, but OS update disruptiveness increases
Solution Approach 1:
The patent segments the queue control information into separate queues for each CPU core. When a CPU core is halted for OS update, only its specific queue is affected, while other queues continue to process I/O commands normally. This segmentation allows selective isolation of halted cores without disrupting the entire system.
Solution Approach 2:
The patent introduces a queue switching mechanism as an intermediary between the protocol chip and CPU. When a CPU is halted, the system can switch the queue assignment from the halted CPU to an active CPU, thereby mediating the disruption and maintaining continuous I/O processing during OS updates.
2Productivity
If SMP OS with single OS on multiple cores is used, then system resource utilization is improved, but queue switching capability during OS update deteriorates
Solution Approach 1:
The patent implements dynamic queue assignment where queues can be reassigned from halted CPUs to active CPUs during OS updates. The queue control information structure allows flexible reconfiguration of which CPU handles which queues, enabling the system to adapt its resource allocation dynamically based on CPU operational status.
Solution Approach 2:
The patent changes the parameter of queue assignment from a static one-to-one mapping to a dynamic many-to-many relationship. By modifying the queue control information parameters, the system can redirect queues from halted to active CPUs, maintaining productivity during OS updates in SMP environments.
3Ease of manufacture
If CPU is halted for OS update, then OS maintenance is improved, but I/O processing continuity deteriorates
Solution Approach 1:
The patent performs preliminary actions by pre-configuring multiple queues with backup CPU assignments. Before a CPU is halted for OS update, the system already has alternative queue assignments ready. When halting occurs, the queue switching mechanism can immediately redirect to pre-prepared alternative queues, minimizing interruption to I/O processing.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining multiple active queues that can take over from halted CPUs. The queue control information structure enables seamless transition of I/O processing from halted to active CPUs, keeping the storage system operational and continuous during OS maintenance activities.
Data Source
AI summary
Provided is a storage system and a storage system management method that are capable of providing continuous I/O processing by switching a queue used for I/O control on a controller side. The storage system includes a first protocol chip, a second protocol chip, a first controller, and a second controller. The first protocol chip and the second protocol chip receive I/O commands from a host. The first controller includes a first CPU. The second controller includes a second CPU. In accordance with an instruction from the first controller, the first protocol chip halts the first CPU, and switches a Qset for sending the I/O commands received by the first protocol chip from Qset 11 to Qset 12.