Auxiliary Bus Master Circuit Preventing Burst Transfer Interruptions
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Solution Overview
Problem
In systems with multiple bus masters, high priority data transfers are often interrupted by low priority data transfers during burst operations, despite priority settings, leading to inefficiencies in data transfer times.
Innovation Solution
An auxiliary bus master circuit is introduced that prioritizes high priority data transfers by controlling access to the bus, using a control circuit to manage access requests and prevent low priority interruptions through dummy data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high priority degree master circuit performs burst transfer, then data transfer speed is improved, but low priority degree master circuits may still interrupt the bus access, causing transfer completion time to increase
Solution Approach 1:
The auxiliary bus master circuit performs preliminary actions by monitoring the bus status and preparing to issue access requests. When the bus becomes available, it immediately issues requests to prevent interruptions, ensuring that high priority transfers complete without delay from low priority circuits.
Solution Approach 2:
The auxiliary bus master circuit acts as an intermediary between the high priority degree master circuit and the bus system. It monitors bus availability and controls access requests, preventing low priority circuits from interrupting high priority transfers while maintaining system arbitration protocols.
2Productivity
If priority arbitration is implemented to give preferential access to high priority bus masters, then data transfer priority is improved, but low priority transfers may still occur during high priority burst operations, reducing overall efficiency
Solution Approach 1:
The auxiliary bus master circuit implements feedback by continuously monitoring the bus status signals and the operation status of high priority degree master circuits. Based on this feedback, it dynamically adjusts its access request timing to prevent interruptions during critical burst transfer periods.
Solution Approach 2:
The system performs preliminary assessment of bus availability and high priority circuit operation status before allowing low priority access. The auxiliary bus master circuit prepares access requests in advance and issues them only when it determines the bus is available and high priority circuits are not actively transferring data.
Data Source
AI summary
An auxiliary bus master circuit is connected or connectable to a bus in a system in which a high priority degree master circuit having a bus access right having a high degree of priority and a low priority degree master circuit having a bus access right having a lower degree of priority than the high priority degree master circuit are connected to one bus, and the auxiliary bus master circuit includes a control circuit that outputs an access request signal for requesting an access right from the bus, based on a timing for outputting at least one of high priority degree master signals being signals exchanged by the high priority degree master circuit through the bus.