Anti-ferroelectric Capacitor Memory Cell Leakage Compensation

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Solution Overview

Problem

Increasing retention time in embedded Dynamic Random Access Memory (DRAM) cells is challenging due to transistor leakage and limited voltage storage, which affects the ability to preserve information over time.

Innovation Solution

The implementation of anti-ferroelectric (AFE) memory cells, specifically the 2T-1AFE-CAP memory cell configuration, which uses an AFE capacitor with nonlinear behavior to boost charge on the storage node, enhancing retention time and scalability, while minimizing the impact of transistor leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If conventional DRAM cells are used, then the structure is simple and manufacturing is easier, but retention time is limited due to transistor leakage and limited voltage storage

Engineering Contradiction:
Improveretention timeVSAvoidvoltage storage stability
Core Design Contradiction:
Duration of action of moving objectVSReliability

Solution Approach 1:

The patent changes the electrical parameters of the memory cell by introducing an anti-ferroelectric capacitor with nonlinear C-V characteristics. This capacitor provides voltage boosting capability, where a small voltage change on one electrode results in a larger voltage change on the other electrode, thereby extending retention time without requiring larger capacitor dimensions

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure combining anti-ferroelectric material with standard DRAM components. The anti-ferroelectric layer is integrated into the capacitor structure, creating a hybrid system that leverages the nonlinear electrical properties of anti-ferroelectric materials while maintaining compatibility with existing DRAM manufacturing processes

Inventive Principle:
Principle #40Composite materials

2Duration of action of moving object

If capacitor size is increased to improve voltage storage, then retention time improves, but device area increases and scalability decreases

Engineering Contradiction:
Improveretention timeVSAvoidmemory cell area
Core Design Contradiction:
Duration of action of moving objectVSArea of stationary object

Solution Approach 1:

The patent exploits the nonlinear C-V characteristics of anti-ferroelectric materials to achieve voltage boosting without increasing capacitor physical dimensions. The voltage boosting effect allows standard-sized capacitors to provide enhanced voltage storage and extended retention time, thereby maintaining high memory cell density

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic voltage boosting capability through the anti-ferroelectric capacitor's nonlinear response. The capacitor dynamically adjusts its effective capacitance based on the applied voltage, providing voltage amplification that extends retention time without requiring static increases in capacitor size

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If transistor gate length is reduced to improve density, then manufacturing precision requirements increase and transistor leakage worsens

Engineering Contradiction:
Improvememory densityVSAvoidtransistor leakage
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent converts the harmful effect of transistor leakage into a beneficial outcome. By using anti-ferroelectric capacitors with voltage boosting capability, the system compensates for charge loss due to leakage. The nonlinear C-V characteristics provide automatic voltage restoration, maintaining logic state distinguishability even in the presence of leakage currents from scaled transistors

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The AFE memory cells increase retention time, improve scalability, and allow for higher density memory arrays, particularly compatible with short gate length technology nodes, by effectively boosting the storage node voltage and maintaining distinguishable logic states.

Implementation Method 1

an anti-ferroelectric (AFE) capacitor with nonlinear behavior to boost charge on the storage node

Methodology Applied
Scientific EffectNonlinear dielectric behavior: Dielectric Permittivity

Data Source

PatentUS11355504B2Anti-ferroelectric capacitor memory cell
Publication Date: 2022.06.07 INTEL CORP
  • US11355504B2 patent drawing
  • US11355504B2 patent drawing
  • US11355504B2 patent drawing

AI summary

Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.