Solid-State Devices TRIZ Cases

A foldable display screen uses patterned organic layers to fill through-holes between inorganic and metal stacks.

Localized doping creates a p-n junction in the channel, reducing leakage current and improving the ON/OFF ratio.

A light-emitting device package defines a recess housing a spaced-apart light-absorbing member with an exposed upward-facing surface.

Curved semiconductor layers extend channel length to improve gate voltage control while minimizing process variations in OLED displays.

Local quality and parameter changes adjust discharge amounts to suppress luminance unevenness and color mixture in organic electroluminescent displays.

A thermal print head uses a recessed heat storage region to accumulate energy.

Parallel current paths in a memory cell adjust conductivity by 100 times within narrow temperature ranges, resolving stability issues in non-volatile storage.

Planar alignment electrodes replace mechanical protrusions in the pixel structure, eliminating light leakage while maintaining an enlarged viewing angle range.

A display apparatus uses intermediary alignment marks to guide precise placement of micro light-emitting diode elements on a driving substrate.

Polysilicon alignment marks bridge frontside and backside processing to resolve color filter alignment mismatches in backside illuminated image sensors.

A double trench process forms side contacts exposing one sidewall of a second trench to create buried bit lines.

Segmented tantalum oxide layers eliminate forming processes and slow switching speeds, delivering high-speed rewritability.

An amorphous oxide electrode absorbs ultraviolet light to protect the light-receiving layer.

Segmented sacrificial structures mediate coating thickness to prevent overflow and maintain critical dimensions in dense layouts.

A reflective structure uses dielectric films with ascending refractive indices to enhance total reflectivity across visible light wavelengths.

A mold uses vacuum adsorption through a through-hole to hold a substrate while forming conductive bumps in precision grooves.

A conductive projection liner between the bottom electrode and phase-change material establishes a stable resistive current path.

A transparent array substrate features a pixel electrode connected via a contact hole that partially exposes the drain electrode.

CTE-matched ceramic substrates reduce lattice mismatch and thermal stress, enabling thicker GaN layers and higher device yields.

Separating bit line and supply voltage wirings reduces voltage drop while curved word lines increase contact area for uniform writing current.

An RC delay circuit triggers a MOS transistor to discharge power source noise, suppressing erroneous operations without enlarging the protection area.

PECVD deposition using argon and hydrogen gas creates smooth silicon films that resolve high compressive stress and roughness issues in 3D memory stacks.

A subpixel structure with a buffer layer and storage electrode prevents electrical shorts and current degradation in flexible organic light emitting displays.

Integrated 45-degree mirrors on the lead frame minimize spacing and reduce light signal loss during optical coupling.

Dual-layer define layers with varying etch rates contain luminescent ink to prevent adjacent pixel spilling and reduce mask complexity.

Optoelectronic semiconductor device with electrode junction reflectivities below 20 percent on a matrix circuit substrate.

A method for fabricating array substrates reduces photolithography steps by patterning a first metal layer to form gate lines and pads.

Adjusting bonding wire parameters compensates for parasitic resistance, maintaining accurate current mirroring despite wiring variations.

A backside illumination CMOS image sensor uses a PN junction region on the light incident surface to hold charges effectively.

A protection film with a high acid etching rate covers an inorganic insulating film to enable continuous electrode formation on the photoelectric conversion layer.

A fluidic assembly method positions emissive elements into substrate wells using high-variance local forcing to control microcomponent velocity and orientation.

Segmented electrode layers with meltable fuse connections isolate short circuits, preventing widespread failure and maintaining efficiency.

Dummy bumps create a single electrical path between stacked chips, enabling early detection of connection failures without testing every signal TSV.

Excimer laser annealing creates a polycrystalline p-n junction that minimizes reset current while maintaining high density crosspoint architecture.

A multi-stack organic light emitting device merges charge generation and electron transport layers into a single functional unit.

Anti-ferroelectric capacitor memory cells boost storage node voltage via nonlinear dielectric behavior, extending retention time despite transistor leakage.

Patterning insulating layer to form protrusions guides planarization of memory device trenches.

Segmented pixel groups and transmission areas enable sensor integration without compromising light transmittance or resolution.

A conductive pattern with an opening applies voltage to a second electrode in the non-display area of an electroluminescent display.

Side-by-side I/O logic and buffer regions reduce pad area without compromising ESD protection or power supply characteristics.

Lenses in a transparent cover focus light onto sensor chiplets adjacent to the display, reducing apparatus thickness while maintaining high resolution.

Textured backside-illuminated imagers diffuse light to increase absorption path length, overcoming silicon's limited infrared detection.

A compact optoelectronic device stacks axial three-dimensional light-emitting diodes above a control circuit using vertical wire bonds.

Relocating wiring from twisting beam portions to stable support structures prevents continuity failures and simplifies manufacturing.

Adjusting isolation layer depth around green pixels reduces light leakage noise while managing manufacturing complexity.

Vertical stacking of control gates and charge trapping layers in a TFT MONOS memory cell maintains capacitance while scaling device geometry.

A TFT-LCD pixel structure uses a gray tone mask to form gate, active, and drain patterns in one exposure step.

An OLED overcoating layer with convex and concave portions directs light extraction through refractive index variations.