Planarizing Insulating Layer for 3D Memory Trenches

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Solution Overview

Problem

The integration density of two-dimensional non-volatile memory devices is limited, prompting the development of three-dimensional non-volatile memory devices with stacked memory cells, but existing manufacturing methods struggle to enhance operational reliability and structural stability.

Innovation Solution

A method of manufacturing a semiconductor device involving the formation of stacked structures with trenches of varying depths, filled with insulating layers and patterned to create protrusions, which are then planarized to improve structural integrity and reduce manufacturing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensional stacked structures are formed to increase integration density, then memory capacity is improved, but structural stability and operational reliability deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidoperational reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The contact region is divided into multiple trenches (first trench adjacent to cell region, second trench apart from cell region) with different depths and widths. This segmentation allows each trench to be independently optimized for its specific function, improving overall structural stability while maintaining high integration density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the contact region are assigned different trench configurations - the first trench has specific dimensions optimized for adjacent to cell region functionality, while the second trench has different dimensions optimized for apart from cell region functionality. This local differentiation enhances operational reliability without compromising integration density.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If trenches of different depths are formed in contact region, then manufacturing flexibility is improved, but process complexity increases

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidprocess complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The contact region etching process is segmented into multiple stages, with each stage creating trenches of specific depths at specific locations. This segmentation provides manufacturing flexibility to optimize each trench independently while keeping the overall process manageable through systematic progression.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The solution introduces depth as an additional dimension of variation in trench configuration, beyond just lateral positioning. By controlling trench depth independently for different regions, the method achieves greater manufacturing flexibility without proportionally increasing process complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If insulating layer is patterned to form protrusions corresponding to trenches, then structural precision is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvestructural precisionVSAvoidmanufacturing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The insulating layer is patterned to form protrusions that preliminarily define the trench positions and dimensions before the actual trench etching. This preliminary action establishes precise structural references that guide subsequent processing steps, improving overall manufacturing precision while organizing the complexity into manageable sequential stages.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protrusions formed in the insulating layer serve as intermediary structures that mediate between the design specifications and the final trench configurations. These protrusions act as templates or guides that translate abstract design requirements into concrete physical structures, enhancing precision without directly increasing final device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11587941B2Method of planarizing insulating layer for memory device
Publication Date: 2023.02.21 SK HYNIX INC
  • US11587941B2 patent drawing
  • US11587941B2 patent drawing
  • US11587941B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.