TFT MONOS Memory Cell Scaling via 3D Stacking
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Solution Overview
Problem
Conventional techniques face challenges in scaling down memory cell size without reducing memory capacitance per unit area, limiting the development of high-density memory devices, and existing memory cell structures have limitations in scalability, memory capacity, and integration into three-dimensional arrays.
Innovation Solution
The development of a thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structure with a substrate, insulation layers, source/drain regions, polysilicon layers, and an oxide-nitride-oxide (ONO) charge trapping layer, allowing for three-dimensional integration and compatibility with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional memory cell structures are used, then manufacturing processes are simpler, but device geometry cannot be scaled down below certain limits
Solution Approach 1:
The patent implements a three-dimensional memory cell structure with vertically stacked components including control gates, charge trapping layers, and source/drain regions arranged in multiple layers. This vertical stacking approach enables continued scaling of device geometry by utilizing the third dimension (height) rather than relying solely on planar dimensions, thereby overcoming the limitations of conventional two-dimensional memory structures.
2Productivity
If device size is reduced to increase circuit density, then more devices fit on each wafer, but manufacturing process limits are reached
Solution Approach 1:
The memory cell is segmented into distinct functional layers including control gates, ONO charge trapping layers, source/drain regions, and tunnel oxides. Each layer can be independently formed and optimized using standard semiconductor fabrication processes such as CVD, PVD, and etching. This segmentation allows the complex 3D structure to be manufactured using existing process technologies without requiring breakthrough manufacturing capabilities.
Solution Approach 2:
The patent employs a nested layer structure where control gates are positioned above and below the charge trapping layer, with source/drain regions embedded within insulating layers. This nested arrangement maximizes the use of available vertical space and enables higher device density within the same footprint while maintaining manufacturability through sequential layer deposition and patterning.
3Area of moving object
If memory cell size is scaled down, then area is reduced, but memory capacitance per unit area decreases
Solution Approach 1:
By transitioning from planar to three-dimensional memory cell architecture with vertically stacked control gates and charge trapping layers, the patent increases the effective capacitance-forming area without increasing the planar footprint. The vertical stacking allows multiple capacitance-contributing interfaces to be packed within the same area, maintaining memory capacitance per unit area even as cell dimensions are reduced.
4Quantity of substance
If three-dimensional memory arrays are formed, then memory capacity increases, but device complexity increases
Solution Approach 1:
The patent designs a universal memory cell structure where control gates, charge trapping layers, and source/drain regions can be replicated and stacked to form three-dimensional arrays. The same basic cell architecture serves multiple functions: storage, addressing, and scaling. This universality allows complex 3D arrays to be built from standardized modular units, reducing the overall system complexity compared to custom-designed 3D structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-density, reliable memory storage with small geometric cell size, low leakage current, and efficient charge retention, while maintaining compatibility with conventional CMOS processes and allowing for the formation of three-dimensional memory arrays.
Implementation Method 1
an oxide-nitride-oxide (ONO) charge trapping layer
Data Source
AI summary
A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. The dielectric layer is associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an oxide-nitride-oxide (ONO) layer overlying the P− polysilicon layer; and at least one control gate overlying the ONO layer. The control gate may be made of a metal layer or a P+ polysilicon layer.