I/O Cell Layout Area Reduction via Horizontal Arrangement
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Solution Overview
Problem
Semiconductor integrated circuit devices face challenges in reducing the area of I/O cell regions without increasing the width, as decreasing the height of I/O cells leads to increased wiring resistance and compromised ESD and power supply characteristics.
Innovation Solution
The I/O logic and buffer regions are arranged side by side in a direction parallel to the core region, overlapping with the pad region, to decrease the height of I/O cells while preventing an increase in width, thereby reducing the overall area of the I/O cell and pad regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the height of I/O cells is decreased to reduce the area of pad regions, then the area of I/O cells is reduced, but the wiring resistance increases and ESD protection characteristics are compromised
Solution Approach 1:
The patent changes the arrangement dimension of I/O cells from a vertical stacking layout to a horizontal side-by-side layout parallel to the core region. This dimensional change allows the I/O logic and buffer regions to be arranged side by side rather than stacked, reducing the height of I/O cells and consequently the area of pad regions while maintaining adequate wiring lengths and ESD protection characteristics through the extended horizontal arrangement
2Area of stationary object
If the height of I/O cells is decreased to reduce the area of pad regions, then the area of I/O cells is reduced, but the power supply characteristics are compromised
Solution Approach 1:
The patent applies dimensional change by arranging I/O logic and buffer regions side by side in a direction parallel to the core region, extending the arrangement horizontally rather than vertically. This reduces the height of I/O cells and the overall area of I/O cells while maintaining adequate power supply characteristics through the extended horizontal configuration that preserves necessary wiring lengths
3Area of stationary object
If I/O cells are arranged in a zigzag pattern to accommodate more I/O cells and pads, then the area efficiency is improved, but the manufacturing complexity and design time increase
Solution Approach 1:
The patent extracts the zigzag arrangement pattern and replaces it with a simpler linear arrangement where I/O cells are positioned side by side in a straight line parallel to the core region. This extraction of the complex zigzag pattern reduces layout complexity and design time while still achieving efficient area utilization through the streamlined horizontal arrangement
Solution Approach 2:
Instead of arranging I/O cells in a zigzag pattern that winds back and forth, the patent inverts the approach by using a direct linear arrangement parallel to the core region. This inversion from a complex curved path to a simple straight line reduces manufacturing complexity while maintaining area efficiency
Data Source
AI summary
A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.