Phase Change RAM Word Line Contact Area Optimization
Solution Overview
Problem
Conventional phase change RAM devices have complex layouts due to the integration of metal wirings for bit lines and supply voltages, which limits integration density and increases voltage drop, affecting the uniformity of writing current for phase change in the PCM layer.
Innovation Solution
The phase change RAM device separates the first metal wiring for the bit line from the second metal wiring for supply voltage, with the latter having a wider width to reduce voltage drop and ensure uniform writing current, and features a T-shaped active area and curved word line to enhance contact areas and current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If metal wirings for bit line and supply voltage are integrated in conventional phase change RAM devices, then the device structure is compact, but the layout becomes complex and integration density is limited
Solution Approach 1:
The patent divides the metal wiring system into separate components: bit line wiring and supply voltage wiring are routed through different pathways (source/drain regions versus separate contact holes), eliminating the need for complex integrated layouts while maintaining compact device structure
Solution Approach 2:
The patent utilizes vertical stacking and multi-layer routing to separate bit line and supply voltage paths in the vertical dimension, allowing both functions to coexist without lateral interference, thereby simplifying the overall layout while improving integration density
2Reliability
If metal wirings for bit line and supply voltage are integrated in conventional phase change RAM devices, then the device structure is compact, but voltage drop increases and writing current uniformity deteriorates
Solution Approach 1:
The patent segments the current path by providing separate supply voltage contact holes and bit line contact holes, allowing independent optimization of each pathway to minimize voltage drop and ensure uniform writing current distribution across the phase change material
Solution Approach 2:
The patent applies different wiring configurations to different regions: supply voltage is applied through wider contact holes and dedicated voltage lines in regions requiring high current, while bit line signaling uses separate optimized pathways, ensuring each region receives appropriate electrical characteristics for its function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the operational speed and integration density of the phase change RAM device by reducing voltage drop and ensuring uniform writing current for phase changes in the PCM layer, thereby enhancing the device's performance.
Implementation Method 1
the phase change layer interposed between bottom and top electrodes undergoes phase change from the crystalline state to the amorphous state as electric current flows between the bottom and top electrodes
Implementation Method 2
such a chalcogenide layer is a compound layer including Ge, Sb, and Te. The chalcogenide layer undergoes phase change between an amorphous state and a crystalline state as current, that is, joule heat is applied thereto
Data Source
AI summary
A phase change RAM device, has a first metal wiring for a bit line that is separated from a second metal wiring for applying a supply voltage. A method for fabricating the phase change RAM device includes the steps of forming an isolation layer formed so as to define a T-shaped active area in the semiconductor substrate, forming a word line formed on the active area of the semiconductor substrate including the isolation layer, forming source/drain areas formed at both sides of the word line in the active area, forming an insulating interlayer on entire surface of the semiconductor substrate so as to cover the word line, and forming a first tungsten plug in a portion of the insulating interlayer on the source area and a second tungsten plug in a portion of the insulating interlayer on the drain area.