GaN Integrated Circuit on CTE-Matched Engineered Substrate
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Solution Overview
Problem
Wide band gap semiconductor devices, such as gallium nitride (GaN), face manufacturing challenges due to lattice mismatch and different coefficients of thermal expansion between GaN and carrier substrates, leading to defects, strains, and increased costs.
Innovation Solution
A gallium nitride based integrated circuit architecture is developed using an engineered substrate with CTE-matched ceramic polycrystalline wafers, allowing for thicker, higher quality epitaxial layers on larger wafers, enabling monolithic integration of multiple devices and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GaN is deposited on a semiconductor carrier substrate with different lattice structure, then GaN layers can be formed, but defects, dislocations, and strains are created that negatively impact device yields and performance
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the carrier substrate and the GaN layers. This buffer layer serves as a transition medium that reduces lattice mismatch and minimizes defect propagation, thereby maintaining ease of manufacture while improving device yields and performance
Solution Approach 2:
The patent modifies the substrate parameters by selecting carrier substrates with lattice constants closer to GaN and by controlling buffer layer thickness and composition. These parameter changes reduce lattice mismatch and thermal expansion differences, decreasing defects and dislocations while enabling high-quality GaN layer formation
2Temperature
If GaN layers and carrier substrate have different coefficients of thermal expansion, then thermal processing can be performed, but the GaN may crack or delaminate and the carrier substrate may break
Solution Approach 1:
The buffer layer acts as a thermal stress buffer, absorbing expansion mismatches between the GaN layers and carrier substrate during thermal processing. This intermediary layer prevents crack propagation and delamination while maintaining structural integrity at high temperatures
Solution Approach 2:
The patent selects carrier substrates with thermal expansion coefficients matched to GaN and optimizes buffer layer properties to accommodate thermal stress. These parameter changes enable thermal processing while preventing structural failure
3Ease of manufacture
If different CTEs between GaN and carrier substrate are present, then GaN devices can be manufactured, but substrate wafer size is limited preventing scale and cost reduction
Solution Approach 1:
The patent changes the substrate parameter by using CTE-matched carrier substrates and optimized buffer layers, which eliminates the thermal expansion mismatch that previously limited wafer size. This enables manufacturing on larger substrate wafers, achieving scale and cost reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases wafer diameter and epitaxial layer thickness, reducing defects and costs, and enabling more complex circuitry and higher device integration, improving performance and scalability of GaN-based devices.
Implementation Method 1
The different CTEs restrict substrate wafer size limiting scale... utilizing embodiments of the present invention, increases in wafer diameter and epitaxial layer thickness are achieved
Implementation Method 2
growing a first set of III-N epitaxial layers coupled to the single crystal layer... growing a second set of III-N epitaxial layers coupled to the first set of III-N epitaxial layers
Data Source
AI summary
A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.