Array Substrate Fabrication Reducing Photolithography Steps
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Solution Overview
Problem
The existing methods for fabricating array substrates for LCDs require multiple photolithography steps, leading to increased time and cost, and are not suitable for larger display sizes due to resistance issues with continuous conductive lines.
Innovation Solution
A method that reduces the number of photolithography steps by patterning a first metal layer to form gate lines and data lines, followed by forming insulating, semiconductor, and ohmic contact layers, and then patterning these layers to create semiconductor structures and via holes, ultimately forming pixel electrodes and storage capacitors with reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography steps are used to pattern conductive layers, then manufacturing precision is improved, but production time and cost increase
Solution Approach 1:
The patent combines multiple photolithography steps into a single step by using a first photolithography process to simultaneously pattern the gate line, gate electrode, and pad from a single continuous conductive layer. This merging of operations reduces the total number of photolithography steps from six to fewer, thereby decreasing production time while maintaining the required patterning precision through careful mask design and single-step exposure.
2Reliability
If continuous conductive lines are used for scan and signal lines, then electrical connectivity is improved, but resistance increases for larger display sizes
Solution Approach 1:
The patent segments the continuous conductive layer into distinct functional regions (gate line, gate electrode, and pad) while maintaining electrical connectivity. By forming these elements from a single continuous layer that is strategically patterned, the design ensures low-resistance pathways for signal transmission while adapting to larger display sizes. The segmentation allows optimization of each region's electrical characteristics without requiring additional conductive layers.
3Loss of energy
If additional conductive layers are formed to reduce resistance, then signal loss is reduced, but device complexity and fabrication steps increase
Solution Approach 1:
The patent merges the functions of multiple conductive elements into a single continuous conductive layer that is patterned in one photolithography step. This approach maintains the electrical performance benefits of multiple layers (by using the full thickness of one layer) while avoiding the fabrication complexity of stacking and aligning multiple thin layers. The single-layer design reduces the number of deposition and patterning steps required.
4Manufacturing precision
If six photolithography steps are used for complete fabrication, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent merges multiple patterning operations into a reduced number of photolithography steps by carefully designing the mask and exposure process to form the gate line, gate electrode, and pad simultaneously from a single continuous conductive layer. This consolidation maintains the precision required for TFT fabrication while significantly improving productivity by reducing the total cycle time and number of process steps.
Data Source
AI summary
Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating layer, a semiconductor layer, and an ohmic contact layer are formed over the substrate to cover the gate line, the gate electrode and the pad. The ohmic contact layer, the semiconductor layer, and portions of the insulating layer are patterned by a second photolithography to forming a semiconductor structure over the substrate and a via hole in the insulating layer over the pad to exposing a part of the pad.