AFSM PLL Divider Using CMOS Cells for Low Jitter Clocks
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Solution Overview
Problem
Existing high-frequency PLL clock divider circuits struggle to accurately divide clock signals above 1 GHz using standard library cells, resulting in speed limitations and high clock jitter, requiring custom-designed logic circuits and costly layouts.
Innovation Solution
A clock divider circuit utilizing an asynchronous finite state machine (AFSM) configured as a counter and programmable circuitry with a delta-sigma modulator, implemented with static CMOS library cells, to achieve dynamic divide ratios and low jitter, enabling division of frequencies up to 1.5 GHz with fine programming steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard library logic cells are used in clock divider circuits, then ease of manufacture and design time are improved, but operating speed is limited to below 1 GHz and clock jitter increases
Solution Approach 1:
The clock divider is segmented into multiple stages: a high-speed division stage using a small modulus counter (dividing by 2, 3, or 4) that operates at the full VCO frequency, and a second division stage that operates at the lower intermediate frequency. This segmentation allows each stage to operate within its optimal speed range, enabling the overall circuit to handle frequencies above 1 GHz while using standard library cells.
Solution Approach 2:
The first division ratio is made dynamically selectable among multiple values (2, 3, or 4) based on the operating conditions and frequency range. This dynamic adaptation allows the circuit to optimize its performance for different input frequencies, maintaining low jitter and high accuracy across a wide frequency range while using standard library components.
2Speed
If custom-designed logic circuits are used to achieve high frequency operation above 1 GHz, then operating speed is improved, but device complexity and design costs increase
Solution Approach 1:
The clock divider circuit is designed to be universally applicable across a wide frequency range (above 1 GHz) using standard library cells that can be reused in multiple contexts. The same basic circuit architecture and cell types can handle different frequency ranges by adjusting the division ratios, eliminating the need for custom-designed circuits for each frequency band and reducing overall device complexity.
3Device complexity
If single-stage high frequency division is used, then device complexity is reduced, but measurement precision and clock jitter increase
Solution Approach 1:
The division process is segmented into multiple stages where the first stage divides the high-frequency VCO signal by a small integer (2, 3, or 4) to produce an intermediate frequency signal with lower jitter, and the second stage performs further division at this lower frequency. This multi-stage approach reduces the jitter that would accumulate in a single-stage divider while keeping the overall circuit complexity manageable through modular design.
Data Source
AI summary
A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal (CLK) for producing information representative of a plurality of phase signals (F0,F1,F2,F3) each of which is a divided-down representation of the input clock signal (CLK) and each of which is phase-shifted by a predetermined amount with respect to another of the phase signals (F0,F1,F2,F3). Programmable circuitry (22) operates in response to both dynamic divide ratio information (DIV_RATIO) and the information representative of the plurality of phase signals (F0,F1,F2,F3) so as to generate an output clock signal (CLKOUT) that is divided down according to both the dynamic divide ratio information and the information representative of the plurality of phase signals (F0,F1,F2,F3).