Continuously Circulated Pulse Counters TRIZ Cases
- Remote Driver Circuit Using Counter-Based Voltage Switching
A counter-driven receiver and resistor network switch device states from any remote signal without pairing, decoding, or complex circuitry.
- Frequency Divider Circuit for Low-Noise Non-Overlapping Clocks
Using staged latches and logic gates, this circuit generates non-overlapping clocks with lower power, phase noise, and die area.
- Clock Generator Phase Setting for IC Timing Convergence
Initial phase settings based on clock path distance and load keep IC functional clocks synchronized with less buffering and lower overhead.
- Pulse Recirculating Circuit for Efficient High-Power Microwave Generation
Unradiated antenna energy is filtered, delayed, and fed back through a nonlinear transmission line to boost microwave pulse efficiency and cut heat.
- Recirculating Microwave Pulses Through a Nonlinear Transmission Line
A diode, low-pass filter, and delay line recover unradiated antenna energy and feed it back for more efficient high-power microwave pulses.
- AC-Coupled Local Oscillator Divider for Stable I/Q Locking
AC coupling and reference current biasing stabilize local oscillator divider locking and cut phase shift between LO input and I/Q outputs.
- FLT N-State Cryptographic Circuits for Unpredictable Switching
Finite Lab Transform reshapes n-state switching in cryptographic circuits to reduce predictability and strengthen resistance to classical and quantum attacks.
- Display Data Transmission Circuit for Multi-Mode Serial Conversion
A unified serial-to-parallel path handles 1-bit, 3-bit, and 4-bit display data modes, cutting separate control paths and circuit complexity.
- Frequency Divider Circuit with Switchable LO Duty Cycles
Controllable regenerative cells let one frequency divider switch between 25% and 50% LO duty cycles while cutting die area and power.
- On-Die Clock Jitter Generator for Memory Verification
An integrated jitter generator adds controlled clock delay and randomness inside a memory chip, enabling accurate verification without external test access.
- Multi-Modulus Divider Initialization for Deterministic Phase Alignment
Resetting divider latches to known states enables deterministic start-up phase alignment for high-frequency clock division up to 50 GHz.
- Single-Path Clock Pulse Generator for At-Speed Test Alignment
A shared divider, phase shifter, and multiplexer generate functional and at-speed test clocks while cutting area, power, and alignment complexity.
- Pulse Recirculating Microwave Circuit for High-Efficiency Power Generation
Unradiated antenna energy is delayed and fed back through a recirculating circuit to boost microwave output efficiency and cut heat loss.
- NVFF Monotonic Counter Architecture for Lower Memory Cell Wear
Using NVFF stages with paired memory cells and selective updates, this case cuts program/erase wear and extends monotonic counter lifespan.
- On-Die Jitter Generator Using Phase Mixing for Memory Validation
Random phase mixing and delayed clock paths generate on-die jitter, enabling memory validation without external verification hardware.
- Configurable Ring Frequency Divider for Multiple Clock Ratios
A ring of configurable divider stages enables multiple clock ratios from one reference signal while limiting IC area, complexity, and power.