NVFF Monotonic Counter Architecture for Lower Memory Cell Wear
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Solution Overview
Problem
Traditional monotonic counters require excessive program/erase cycles on memory cells, leading to premature failure due to the high number of updates needed for long-term continuous counting in financial and security systems, as they can only support a limited number of cycles before degradation.
Innovation Solution
Implementing a monotonic counter using non-volatile flip-flop (NVFF) stages with pairs of non-volatile memory cells, where each NVFF counter includes multiple memory cells, reducing the number of updates required for each counting bit by using ring counters like Johnson ring counters, which perform updates efficiently across multiple bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional monotonic counters use single memory cells for each counting bit, then the device complexity is low, but the number of program/erase cycles required exceeds the memory cell lifespan
Solution Approach 1:
The patent divides each counting bit storage into multiple memory cells (pairs of cells per NVFF) instead of using a single memory cell. This segmentation allows the system to distribute update operations across multiple cells, reducing the cycle count on individual cells and extending their operational lifespan.
Solution Approach 2:
The patent changes the operational parameters of the counter by implementing NVFF stages that use pairs of non-volatile memory cells with conditional update logic. The system monitors carry signals and selectively updates only certain memory cells based on the counting state, thereby reducing the total number of program/erase cycles on each individual cell.
2Reliability
If traditional monotonic counters continuously update each counting bit, then the counting function is accurate, but the memory cells undergo excessive wear from frequent updates
Solution Approach 1:
The patent implements partial updates by selectively updating only certain memory cells based on carry signals from lower-order stages. Instead of updating all memory cells on every count transition, the system performs updates only when necessary, reducing overall wear while maintaining accurate counting functionality.
Solution Approach 2:
The patent uses pairs of memory cells as redundant copies for each counting bit. This copying approach allows the system to maintain accurate count values while distributing the update workload, as not all copies need to be updated on every counting operation.
3Reliability
If the monotonic counter uses NVFF stages with pairs of memory cells, then the number of program/erase cycles per cell is reduced, but the device complexity increases
Solution Approach 1:
The patent merges multiple memory cells into NVFF (non-volatile flip-flop) stages that function as unified counting units. By combining pairs of memory cells into functional NVFF blocks with shared control logic, the system manages the increased complexity through modular organization while achieving reduced update cycles per cell.
Data Source
AI summary
A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.