On-Die Clock Jitter Generator for Memory Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for verifying memory device performance against clock jitter rely on external verification devices, which are limited in accessibility and accuracy, especially during manufacturing stages where the memory device is internal to a computing system, leading to incomplete validation of internal component interactions with clock jitter.
Innovation Solution
An on-die jitter generator is integrated into the memory device to create and manage clock jitter, allowing for internal verification of performance by generating a clock signal with jitter, which can be adjusted in distribution and delay to simulate various jitter conditions, enabling comprehensive validation before, during, and after deployment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external verification devices are used to verify memory device performance, then verification can be performed, but accessibility is limited and accuracy is reduced when memory device is internal to computing system
Solution Approach 1:
The memory device includes an integrated jitter generator that enables self-verification of performance under jitter conditions. The device generates its own test signals and measures its own response, eliminating the need for external verification equipment and allowing accurate testing regardless of accessibility.
Solution Approach 2:
The jitter generator acts as an intermediary component within the memory device that introduces controlled jitter into clock signals during verification. This internal intermediary allows the device to simulate adverse conditions and measure performance without requiring external devices to physically access or manipulate the memory device.
2Reliability
If external verification devices are used, then verification activities can be performed, but they are limited to specific stages in manufacturing process
Solution Approach 1:
The integrated jitter generator provides universal verification capability across multiple manufacturing stages and usage scenarios. The same internal circuitry enables verification during manufacturing, after manufacturing completion, and during field operation, making the verification system adaptable to any stage without requiring different external equipment.
3Productivity
If verification is performed using data input/output signals, then operational monitoring can be conducted, but internal component interactions with clock jitter cannot be accurately assessed
Solution Approach 1:
The verification process is segmented into two distinct functions: the jitter generator segment that introduces controlled jitter at the clock signal level, and the performance measurement segment that evaluates internal component responses. This segmentation allows direct observation of internal interactions with jitter while maintaining efficient verification through automated testing.
Data Source
AI summary
A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signal, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.