Multi-Modulus Divider Initialization for Deterministic Phase Alignment
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Solution Overview
Problem
Conventional clock dividers in fifth generation wireless communication systems do not guarantee deterministic phase alignment between the high-frequency source clock signal and the intended-frequency clock signal, particularly at start-up, leading to random phase relationships.
Innovation Solution
A modulus divider apparatus comprising a plurality of latches and logic gates that can be set and reset to ensure deterministic phase alignment, allowing the divider to start dividing on a correct clock edge and operate with programmable integer values, implemented as integrated circuits for high-frequency applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock dividers are used to divide high-frequency clock signals, then clock division function is achieved, but deterministic phase alignment between input and output clock signals cannot be guaranteed
Solution Approach 1:
The patent applies preliminary action by forcing all latches into a predetermined initial state (Q0=Q1=...=QN=0) before the division operation begins. This is achieved through control signals that reset the latches to known states, ensuring that the first output transition occurs at a deterministic time relative to the input clock edge, thereby guaranteeing phase alignment determinism without requiring complex feedback mechanisms.
Solution Approach 2:
The patent introduces control signals as intermediaries that manage the state of latches. These control signals coordinate the initialization and operation of multiple latches, ensuring that they all start from the same known state. This intermediary mechanism simplifies the overall structure compared to complex feedback circuits while maintaining deterministic phase relationships.
2Reliability
If conventional dividers are used at start-up, then clock division operates, but initial transition has random phase relationship with input clock
Solution Approach 1:
The patent eliminates initialization time loss by performing preliminary action - all latches are forced into their initial state (Q=0) synchronously before the division operation starts. This ensures that the first output transition occurs at a predictable time relative to the input clock edge, achieving deterministic phase alignment at start-up without requiring lengthy initialization periods or warm-up cycles.
3Reliability
If multiple latches are used to achieve deterministic phase alignment, then phase consistency is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by giving each latch a specific function in the division sequence while maintaining uniform initialization control. Each latch processes a specific stage of the division operation, but all are controlled by the same initialization mechanism. This localized approach ensures phase consistency across the entire division chain without requiring complex inter-latch coordination circuits.
Solution Approach 2:
The patent changes the state parameter of all latches simultaneously to a predetermined initial value (Q=0) before operation begins. This parameter change approach ensures that all latches start from the same known state, guaranteeing deterministic phase relationships. The simplicity of this parameter initialization method avoids the need for complex feedback or synchronization circuits.
Data Source
AI summary
An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.