Clock Generator Phase Setting for IC Timing Convergence
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Solution Overview
Problem
The integration of tens of billions of transistors in modern integrated circuits leads to complex timing convergence issues, with long-distance transmission and high loads causing violations in setup time and hold time, necessitating additional buffers and clock generators, which increases design complexity and resource overhead.
Innovation Solution
An integrated circuit with a clock source and multiple functional circuits, where clock generators determine initial phases based on transmission distance and load to synchronize clock signals, using time-average-frequency direct period synthesis, eliminating the need for separate delay units and allowing dynamic adjustment of clock signals according to load states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional buffers and clock generators are added to compensate for long-distance transmission and high loads, then clock signal timing requirements are met, but device complexity and resource overhead increase
Solution Approach 1:
The patent changes the parameter of clock signal distribution by introducing initial phase settings for each clock generator. Each clock generator is configured with a specific initial phase value that compensates for transmission distance and load effects, allowing clock signals to arrive at functional circuits simultaneously without adding buffers. This parameter-based compensation resolves the timing convergence issue while maintaining simple circuit architecture.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and setting the initial phases of clock generators before the integrated circuit operates. The initial phases are determined based on transmission distances and load characteristics of different functional circuits, enabling the clock synchronization to be achieved in advance without requiring complex real-time adjustment mechanisms or additional buffering components.
2Productivity
If transmission distance from clock source to functional circuits is increased, then integration density improves, but clock signal timing convergence deteriorates
Solution Approach 1:
The patent uses parameter changes by adjusting the initial phase values of clock generators according to their distance from the clock source. Clock generators serving functional circuits farther from the clock source are assigned different initial phases compared to those closer, compensating for the increased transmission distance. This allows high integration density with long transmission distances while maintaining clock timing convergence through phase parameter optimization.
3Area of stationary object
If multiple clock generators are distributed throughout the integrated circuit, then clock signal distribution coverage improves, but resource overhead increases
Solution Approach 1:
The patent applies universality by making each clock generator multi-functional. Each clock generator not only generates clock signals but also inherently compensates for transmission delays through its initial phase setting, eliminating the need for separate buffer components. This multi-functionality allows wide clock distribution coverage while minimizing the number of clock generators required, as each generator handles both signal generation and timing compensation for its associated functional circuits.
Data Source
AI summary
An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.