Frequency Divider Circuit with Switchable LO Duty Cycles
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Solution Overview
Problem
Existing frequency dividers can only generate fixed duty-cycle LO signals, requiring multiple separate circuits for different duty cycles, leading to increased silicon die area, power consumption, and complexity in transceivers.
Innovation Solution
A single frequency divider circuit with a feedback loop and controllable regenerative cells allows for adjustable duty cycles, enabling generation of multiple duty-cycle LO signals, such as 25% and 50%, using a single circuit architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate frequency divider circuits are implemented to provide different duty cycles (25% and 50%), then both suppression of unwanted even harmonics and higher sensitivity can be achieved, but silicon die area and device complexity increase
Solution Approach 1:
The frequency divider circuit is designed to perform multiple functions by generating different duty cycle outputs (25% and 50%) from a single circuit architecture. The circuit uses controllable regenerative cells that can be selectively activated to produce different duty cycles, eliminating the need for separate dedicated divider circuits for each duty cycle requirement.
Solution Approach 2:
The frequency divider circuit incorporates dynamic control capability through controllable regenerative cells that can be selectively activated or deactivated. This allows the circuit to dynamically switch between different duty cycle modes (25% for receiver sensitivity, 50% for transmitter harmonic suppression) based on operational requirements, making the circuit adaptable rather than fixed.
2Adaptability or versatility
If multiple separate frequency divider circuits are implemented to provide different duty cycles, then both suppression of unwanted even harmonics and higher sensitivity can be achieved, but power consumption increases
Solution Approach 1:
The frequency divider circuit is designed to perform multiple functions by generating different duty cycle outputs (25% and 50%) from a single circuit architecture. The circuit uses controllable regenerative cells that can be selectively activated to produce different duty cycles, eliminating the need for separate dedicated divider circuits for each duty cycle requirement.
Solution Approach 2:
The circuit merges the functionality of multiple frequency dividers into a single integrated circuit by combining controllable regenerative cells within one divider architecture. This consolidation reduces the total power consumption compared to operating multiple separate divider circuits, while still providing the capability to generate different duty cycles as needed.
3Adaptability or versatility
If multiple separate frequency divider circuits are implemented to provide different duty cycles, then both suppression of unwanted even harmonics and higher sensitivity can be achieved, but device complexity increases
Solution Approach 1:
The frequency divider circuit is designed to perform multiple functions by generating different duty cycle outputs (25% and 50%) from a single circuit architecture. The circuit uses controllable regenerative cells that can be selectively activated to produce different duty cycles, eliminating the need for separate dedicated divider circuits for each duty cycle requirement.
Solution Approach 2:
The frequency divider circuit incorporates dynamic control capability through controllable regenerative cells that can be selectively activated or deactivated. This allows the circuit to dynamically switch between different duty cycle modes (25% for receiver sensitivity, 50% for transmitter harmonic suppression) based on operational requirements, making the circuit adaptable rather than fixed.
Data Source
AI summary
A frequency divider is provided which uses common circuitry to switch between different duty cycle outputs. The divider has one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal. Each memory element has a first regenerative cell and a second regenerative cell, and where one of the regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit. The controllable regenerative cell can be selectively activated so that in a first configuration where the controllable regenerative cell is activated an output of the frequency divider circuit has a first duty cycle and in a second configuration where the controllable regenerative cell is deactivated an output of the frequency divider circuit has a second duty cycle.


