Frequency Divider Circuit for Low-Noise Non-Overlapping Clocks
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Solution Overview
Problem
The generation of non-overlapping clock signals typically consumes substantial power and suffers from excessive phase noise, which is not effectively addressed by existing frequency divider technologies.
Innovation Solution
A frequency divider is designed with a series of stages comprising 3-input and 2-input logic gates, differential clock sources, and latches to generate non-overlapping clock signals from overlapping clock signals, reducing power consumption and phase noise by directly producing both overlapping and non-overlapping clock signals within the same circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional frequency dividers are used to generate non-overlapping clock signals, then the clock signals can be produced, but power consumption is substantial and phase noise is excessive
Solution Approach 1:
The frequency divider is divided into multiple stages, where each stage processes a portion of the frequency division task. The first stage generates overlapping clock signals, and the second stage processes these to generate non-overlapping clock signals. This segmentation allows optimization of each stage for specific functions, reducing overall power consumption and phase noise.
Solution Approach 2:
Overlapping clock signals serve as an intermediary between the input clock signal and the final non-overlapping clock signals. The first frequency divider stage generates these intermediate overlapping signals, which are then processed by the second stage. This intermediary approach enables gradual transformation of the clock signals while minimizing power consumption and phase noise accumulation.
2Reliability
If multiple stages of frequency division are implemented, then non-overlapping clock signals can be generated, but device complexity increases
Solution Approach 1:
The frequency divider circuit is designed to perform multiple functions: it generates both overlapping and non-overlapping clock signals, and can operate with different division ratios (e.g., divide-by-3, divide-by-4, divide-by-5). The same basic circuit structure handles different division ratios by adjusting the feedback path, reducing the need for separate circuits for each function and thereby managing complexity.
Solution Approach 2:
The circuit combines the generation of overlapping and non-overlapping clock signals within a unified frequency divider structure. The output of the first stage is directly fed into the second stage without requiring separate independent circuits, and the feedback mechanism is integrated to control the overall division ratio, merging multiple functions into a single cohesive device.
Data Source
AI summary
A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.