On-Die Jitter Generator Using Phase Mixing for Memory Validation
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Solution Overview
Problem
Existing memory device verification methods rely on external devices, which are limited in accessibility and scope, making it challenging to accurately monitor and verify performance against clock jitter within the device during manufacturing and deployment stages.
Innovation Solution
Incorporating an on-die jitter generator within the memory device to create and manage clock jitter, allowing for internal verification of performance across various stages, including manufacturing and customer use, by generating a clock signal with jitter using a phase mixer and random number generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external verification devices are used to verify memory device performance, then verification can be performed at manufacturing stages, but verification accuracy is limited due to inaccessibility to internal device operations
Solution Approach 1:
The memory device includes an on-die jitter generator that enables the device to verify its own performance characteristics. The jitter generator creates controlled jitter conditions internally, allowing the memory device to self-test and self-verify without requiring external verification equipment, thereby improving measurement precision while avoiding additional system complexity
Solution Approach 2:
The on-die jitter generator acts as an intermediary component within the memory device that facilitates verification by generating controlled jitter signals. This internal jitter generator serves as a mediator between the clock signal and the verification process, enabling accurate measurement of jitter effects on memory operations without needing external intervention
2Reliability
If verification is performed only at manufacturing stages using external devices, then device accessibility is maintained, but continuous monitoring across deployment stages is lost
Solution Approach 1:
The on-die jitter generator is pre-configured within the memory device during manufacturing to enable future verification activities. By preparing the verification capability in advance and embedding it in the device, the system ensures that reliability monitoring can continue across all deployment stages without requiring external equipment or complex setup procedures later
Solution Approach 2:
The on-die jitter generator provides universal verification capability that functions across multiple deployment stages including manufacturing, field testing, and customer use. This single internal component serves multiple verification purposes throughout the device lifecycle, maintaining both reliability monitoring and operational simplicity across all stages
3Reliability
If on-die jitter generator is implemented, then continuous verification across all deployment stages is enabled, but device complexity increases
Solution Approach 1:
The jitter generator functionality is merged with the existing memory device architecture, integrating verification capabilities into the standard device structure. By combining the jitter generation function with the memory device's existing clock distribution and control logic, the design improves reliability monitoring while minimizing the increase in overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables comprehensive and continuous validation of memory device performance before, during, and after deployment, improving operational reliability and accuracy by allowing verification at multiple stages without external device access.
Implementation Method 1
the phase mixer to receive the input clock signal and a mix weight control signal and transmit an output clock signal. The phase mixer is configured to randomly mix a first phase of the input clock signal and a second phase of the delayed clock signal together based on the mix weight control signal to create the output clock signal with the jitter
Implementation Method 2
the delay block to receive the input clock signal and transmit the delayed clock signal. The delay block is configured to delay the input clock signal to create the delayed clock signal, where a rising edge of the delayed clock signal occurs at a later time than a corresponding rising edge of the input clock signal
Implementation Method 3
the random number generator to receive the input clock signal and transmit the mix weight control signal. The random number generator is configured to output a random number of N bits, where M bits, as a subset of the N bits, correspond to the mix weight control signal
Data Source
AI summary
A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signals, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.