Configurable Ring Frequency Divider for Multiple Clock Ratios
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Solution Overview
Problem
Existing frequency-divider circuitry lacks flexibility in configuring multiple divider ratios, particularly when more than one divider ratio is needed in a single IC or across different ICs, making it desirable to have improved circuitry that can readily configure the reference clock signal and divider ratio.
Innovation Solution
The implementation of a configurable frequency-divider circuitry with N stages organized in a ring, where each stage is controlled by a reference signal and at least one stage is configurable based on a configuration signal to adjust the divider ratio, allowing for multiple divider ratios to be achieved with the same circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing frequency-divider circuitry is used with fixed divider ratios, then the circuit structure is simple, but the adaptability to configure multiple divider ratios is poor
Solution Approach 1:
The patent implements configurable stages that can dynamically change their operation mode based on configuration signals. Each stage can be configured to operate in different modes (e.g., normal inversion mode, bypass mode, or different delay modes) allowing the overall divider ratio to be adjusted without changing the physical circuit structure. This dynamic reconfigurability resolves the contradiction by enabling multiple divider ratios while maintaining a fixed circuit topology.
Solution Approach 2:
The patent changes the operational parameters of the divider stages through configuration signals rather than changing the circuit structure. By controlling the configuration signals, the same physical circuit can operate with different effective divider ratios. This parameter-based control approach enables adaptability without increasing device complexity.
2Adaptability or versatility
If multiple frequency-divider circuits with different divider ratios are provided, then the adaptability is improved, but the device size and cost increase
Solution Approach 1:
The patent designs each divider stage to be multi-functional, capable of operating in multiple modes depending on the configuration signal. A single universal stage design can function as a normal inverter, a bypass element, or provide different delay characteristics. By making the stages universal, the patent eliminates the need for multiple dedicated circuits for different divider ratios, thereby reducing the integrated circuit area while maintaining the capability to provide multiple divider ratios.
Solution Approach 2:
The patent merges the functionality of multiple separate frequency-divider circuits into a single reconfigurable circuit. Instead of providing separate circuits for different divider ratios, the patent combines them into one circuit with configurable stages that can be arranged in different operational configurations. This merging approach reduces the overall circuit area and component count while achieving the same functional capability.
3Adaptability or versatility
If multiple frequency-divider circuits are provided, then the divider ratio flexibility is improved, but the power consumption increases
Solution Approach 1:
The patent employs dynamic configuration where stages can be switched between active and bypass modes based on the desired divider ratio. When a stage is in bypass mode, it consumes minimal power compared to when it is actively inverting. This dynamic switching capability allows the circuit to optimize power consumption based on the operational requirements, resolving the contradiction between flexibility and power usage.
Solution Approach 2:
The patent extracts the essential functionality from multiple separate circuits and consolidates it into a single reconfigurable circuit. By taking out only the necessary active stages and bypassing the others, the circuit achieves the desired divider ratio with minimal power consumption. Unused stages can be completely bypassed, eliminating their power consumption contribution.
Data Source
AI summary
There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.