Agile Ring Oscillator Clock Control for Adaptive Cycle Timing
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Solution Overview
Problem
Conventional clock generators, such as phase-locked loops (PLLs), lack flexibility in responding to environmental changes like process, voltage, and temperature variations, resulting in fixed clock cycle times that do not adapt to the varying usage patterns of circuits, leading to inefficient power usage and performance.
Innovation Solution
An agile ring oscillator (ARO) system that dynamically adjusts the cycle time of the output clock based on expected usage patterns by varying the number of signal inversions in its ring oscillators, allowing for independent control of high and low phases through control words, enabling the clock frequency to change in response to anticipated activity levels of connected circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional clock generators (PLLs) are used, then stable clock signals can be generated, but the clock cycle time remains fixed and cannot adapt to varying usage patterns, leading to inefficient power usage
Solution Approach 1:
The patent implements a dynamic clock generator that adjusts clock cycle time based on predicted circuit activity. The system uses historical activity data to forecast future usage patterns and dynamically modifies the clock period accordingly, transitioning from fixed to adaptive timing to optimize power consumption while maintaining performance when needed.
Solution Approach 2:
The invention changes the clock cycle time parameter dynamically based on predicted activity. By adjusting the period parameter of the clock signal according to forecasted circuit usage, the system achieves adaptability in power consumption without sacrificing operational performance when activity is anticipated.
2Use of energy by moving object
If conventional clock generators with fixed cycle times are used, then circuit operation is simplified, but power consumption increases because circuits cannot operate at optimal frequencies based on actual usage patterns
Solution Approach 1:
The system performs preliminary analysis of circuit activity patterns to predict future usage. By forecasting activity before it occurs, the clock generator can pre-adjust the cycle time to match anticipated needs, achieving power optimization without requiring complex real-time control mechanisms.
Solution Approach 2:
The invention incorporates feedback mechanisms that monitor actual circuit activity and use this information to refine predictions and adjust clock timing. This feedback loop enables the system to learn from past behavior and continuously optimize power consumption while maintaining appropriate clock frequencies for circuit operation.
3Productivity
If the clock frequency is dynamically adjusted based on usage patterns, then power-to-performance ratio improves, but the clock generator becomes more complex with additional control mechanisms
Solution Approach 1:
By performing activity prediction in advance, the system avoids the need for complex real-time decision-making circuits. The preliminary analysis of usage patterns allows the clock generator to be configured optimally before operation, achieving high performance-to-power ratios with relatively simple control logic.
Solution Approach 2:
The clock generator system serves itself by automatically adjusting its parameters based on predicted activity without requiring external intervention. This self-adjusting capability improves performance-to-power ratio while minimizing the complexity of external control mechanisms needed.
Data Source
AI summary
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.