Agile Ring Oscillator Clock Control for Variable Cycle Timing
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Solution Overview
Problem
Phase-locked loop (PLL) clock generators lack flexibility in responding to environmental changes such as process, voltage, and temperature (PVT) variations, resulting in fixed cycle times that do not adapt to the varying usage patterns of connected circuits.
Innovation Solution
An agile ring oscillator (ARO) system that includes multiple ring oscillators and a controller to dynamically adjust the cycle time of the output clock based on expected usage patterns of connected circuits, allowing for variable cycle times and improved performance-to-power ratio by altering the number of signal inversions in each cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) is used to generate clock signals, then frequency stability is improved, but adaptability to PVT variations and usage patterns deteriorates due to fixed cycle times
Solution Approach 1:
The patent implements dynamic clock cycle time adjustment by using multiple ring oscillators with different propagation delays that can be selectively activated. The system transitions from static PLL-based clock generation to a dynamic architecture where the clock period can be adjusted in real-time based on operational requirements, temperature, voltage, and process variations, thereby resolving the contradiction between stability and adaptability.
Solution Approach 2:
The system changes the fundamental parameter of clock cycle time from fixed to variable by selecting different ring oscillator configurations. By modifying the number of inverting gates in the feedback path and adjusting delay elements, the system achieves multiple clock periods to optimize performance across different operating conditions while maintaining frequency stability through controlled selection of oscillator configurations.
2Device complexity
If a fixed cycle time is used in PLL-based clock generators, then circuit simplicity is maintained, but performance-to-power ratio deteriorates due to inability to adapt to varying usage patterns
Solution Approach 1:
The patent segments the clock generation function into multiple independent ring oscillators, each optimized for specific operating conditions. Instead of a single complex adaptive PLL, the system uses several simpler ring oscillator units that can be independently selected and activated, distributing the adaptability function across multiple simple components rather than one complex centralized controller.
Solution Approach 2:
The system introduces dynamic selection of clock cycle times based on actual usage patterns detected by performance monitoring logic. The controller dynamically switches between different ring oscillator configurations to match operational demands, enabling the circuit to achieve optimal performance-to-power ratio by activating only the necessary oscillator segments rather than running a continuously complex adaptive system.
3Adaptability or versatility
If multiple ring oscillators are used to achieve variable cycle times, then adaptability to usage patterns is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple ring oscillator units into a unified clock generation system with shared control logic and common output infrastructure. By combining the oscillators and their control mechanisms into an integrated architecture, the system achieves variable cycle time capability while minimizing the increase in overall device complexity through资源共享 and functional integration.
Solution Approach 2:
The ring oscillator system is designed with universal components that can serve multiple functions. The same ring oscillator units can generate different clock periods by changing the active feedback path configuration, and the control logic can manage multiple oscillators using similar selection mechanisms, thereby reducing redundant complexity while maintaining high adaptability.
Data Source
AI summary
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.