Aging Tolerant Register File With Gated-Shared-P Circuit
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Solution Overview
Problem
Microprocessor core minimum operating supply voltage (VMIN) is limited by register files, degrading with technology scaling and exacerbated by aging, which affects energy efficiency and design complexity.
Innovation Solution
Implementing an aging-tolerant gated-shared-P circuit with a diode-clamp and a fully-gated contention-free bit-line keeper to reduce aging impact and improve VMIN, allowing for lower supply voltage operation without increasing die area or design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If supply voltage is scaled down to improve energy efficiency, then power consumption is reduced, but the minimum operating voltage (VMIN) increases due to aging effects
Solution Approach 1:
The patent applies preliminary action by proactively reducing the supply voltage to the memory array before aging effects significantly degrade the VMIN. The gated-shared-P circuit is designed to operate at reduced voltage from the outset, preventing the need for higher voltage compensation later in the device lifetime. This allows the system to maintain energy efficiency while accounting for future aging degradation.
Solution Approach 2:
The patent implements beforehand cushioning by designing the memory array with enhanced circuitry (gated-shared-P and controllable read ports) that provides a voltage margin to compensate for aging effects. This cushioning allows the system to operate at lower initial voltages while maintaining reliable operation even after aging degrades the memory cells, effectively decoupling the initial power consumption from the aged VMIN.
2Use of energy by stationary object
If memory array VMIN is lowered to improve energy efficiency, then dynamic power is reduced, but aging effects become more pronounced
Solution Approach 1:
The patent applies dynamics by making the memory array voltage controllable and adaptable. The gated-shared-P circuit and controllable read ports allow the memory to dynamically adjust its operating characteristics. The memory array can operate at lower voltages for energy efficiency while the enhanced circuitry dynamically compensates for aging effects, allowing the system to maintain optimal performance throughout the device lifetime despite voltage scaling.
Solution Approach 2:
The patent implements parameter changes by modifying the memory array's operating parameters (voltage, timing, circuit configuration) to optimize for both energy efficiency and aging tolerance. By changing the circuit topology to include gated-shared-P devices and controllable read ports, the system can operate at reduced voltage parameters while the enhanced circuit design compensates for the increased susceptibility to aging effects that would normally result from such parameter reductions.
3Use of energy by stationary object
If conventional memory designs are used to achieve low VMIN, then energy efficiency is improved, but design complexity increases
Solution Approach 1:
The patent applies universality by designing the gated-shared-P circuit and controllable read ports to serve multiple functions simultaneously. These circuits not only enable reduced voltage operation for energy efficiency but also provide aging compensation, write protection, and read optimization. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in design complexity while achieving multiple benefits.
Solution Approach 2:
The patent implements merging by combining the voltage control, aging compensation, and read/write protection functions into an integrated memory array design. The gated-shared-P circuit merges the functions of voltage regulation, aging compensation, and write protection, while the controllable read ports combine read optimization with aging tolerance. This integration achieves low power operation with enhanced reliability without proportionally increasing design complexity.
Data Source
AI summary
An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.