Digital Storage TRIZ Cases

A refresh controller manages memory cell array blocks to execute hammer refresh operations alongside normal refresh cycles.

A semiconductor device clock buffer circuit generates an internal clock signal only during required periods based on external command signals.

A refresh mechanism updates nonvolatile memory cells and reference cells to maintain accurate resistance windows.

Direct page latch reading verifies non-volatile writes and checks functionality, eliminating long high voltage cycles.

Segmenting memory into banks with dedicated multiplexers limits fan-in to resolve reliability issues.

Unified control logic coordinates processor access across multiple ports to reduce power consumption while maintaining rapid response speed.

A magnetoresistance element control method combines electric field induced reversal with spin injection to accelerate writing speed.

A SRAM design applies a reduced voltage to P channel transistor sources and bodies for read and write assist operations.

A data storage circuit with input and output latches uses dual data lines to control switching devices for state retention.

Dynamic redundancy registers store unverified data words to resolve high write error rates in spin-transfer torque magnetic random access memory devices.

A verification voltage pulse improves RRAM read stability by raising the signal level above standard reading thresholds.

A refresh control unit disables refresh commands during clock synchronization to ensure stable locking completion.

A semiconductor data input buffer generates write data and detects voltage levels during read operations.

A non-volatile static random access memory combines SRAM and NVM components to enable power cutoff during sleep mode while maintaining high-speed access characteristics.

A spin-transfer magnetic memory method uses current-induced domain wall propagation to reorient free layer magnets for robust data storage.

A scannable-latch random access memory merges functional and scan modes to reduce operational overhead.

A shared electrode structure connects multiple magnetic tunnel junction stacks to lower electrical contact resistance within the memory array.

Floating signal lines and applying inhibit voltages to cross-point memory devices increases voltage levels via capacitive coupling.

A memory array design performs bitwise logical operations on multiple operands concurrently using modified cell structures and read word lines.

Segmenting the global bitline into near and far segments lowers capacitance and RC delay, preventing floating states that cause false reads.

Segmented source lines span multiple bit lines to maintain cell selectivity while reducing resistance and eliminating sustained disturb voltages.

Centralized controller tracks memory operations to mitigate row hammer effects without duplicating hardware.

A nonvolatile memory buffer circuit stores critical data attributes to maintain system integrity during power events.

FIFO buffers delay address portions to predict access patterns, allowing circuits to switch unused arrays into sleep mode and reduce cycling power.

Switching word line voltages between read and write modes improves write current while reducing gate oxide stress in common source line STT MRAM.

Complementary bit lines and voltage sense amplifiers eliminate reference cells to resolve overlapping drain current distributions.

A semiconductor memory data I/O unit transfers information between global lines and pads using a multi-purpose register.

A row address control circuit generates local row enable signals only during active bank operations.

Partial block current measurement compensates for shrinking read windows at high temperatures, maintaining calculation accuracy without full array testing.

Dynamic load-based control stabilizes generated voltage across varying loads, reducing ripple and improving sensing margins in memory systems.

Segmented SRAM banks allow parallel data access, reducing processor idle time during sequential operations.

An adder circuit calculates sum voltages from bit line currents in a memristor array, reducing circuit scale by avoiding analog-to-digital conversion.

Multi-port SRAM cell design with separate active regions for pull-down and pass-gate transistors.

Dynamic buffers select contacts to connect memory banks, reducing circuitry complexity and improving signal speed.

Coupling a sense amplifier to bit lines boosts write voltages, resolving low drive failures in dual rail memory without adding circuitry.

Clamping devices limit negative voltage magnitude to prevent unselected bit switch activation during SRAM write operations.

A test method applies stress voltage between bit and plate lines to simultaneously activate cell transistors in ferroelectric memory blocks.

Dissipative coupling layers prevent inadvertent thresholding of unselected memory cells by stabilizing floating pillar voltages.

A bit line clamp voltage generator circuit uses a diode-connected negative channel Field Effects Transistor with resistors to control the sense amplifier input voltage.

A resistive memory device uses a control circuit to enable a distant column selection circuit during read operations.

Shared bulk bias eliminates barrier ribs, reducing device size while maintaining discrimination of active regions.

Shared semiconductor fins merge write and read transistors to resolve the trade-off between access speed and device complexity in DRAM.

Reducing bit line pre-charge voltage to ½ VDD lowers power consumption while maintaining reliable signal detection through differential sensing.

Periphery logic converts mask bits to indices within memory arrays, eliminating off-chip data transfer overhead and reducing energy consumption.

Segmenting the latching circuit with a transmission gate prevents leakage-induced ground boosting and reduces sensing current while improving C-Q delay.

A sensing circuit uses a logic gate and digital feedback loop to latch memory cell states.

Segmenting RAM into sub-memory spaces allows parallel access, resolving bandwidth bottlenecks that limit processing speed in single-port memory systems.

Segmented magnetic tunnel junction elements enable multi-bit storage within a single memory cell through controlled pulse application.

Segmenting memory banks reduces leakage current consumption while maintaining data retention reliability.

Gated-shared-P circuit with diode-clamp reduces aging impact on register files, improving write and read VMIN by 180mV and 120mV respectively.