Memory Array Power Control via FIFO Address Pipelining
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Solution Overview
Problem
In systems with multiple memory cell arrays, putting unused arrays into sleep mode to conserve power is inefficient due to the power consumed in cycling between sleep and standby modes, as these arrays may be accessed again soon, and designers must predict usage at design time to benefit from power savings.
Innovation Solution
Implementing a circuit arrangement with FIFO buffers and control circuits that pipeline memory access requests to determine which arrays to put into sleep mode based on anticipated access, delaying addresses and enable signals to ensure arrays are only cycled into sleep mode when not accessed for a predetermined period, thereby optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory cell arrays are put into sleep mode to save power, then power consumption is reduced, but the power consumed in cycling between sleep and standby modes increases
Solution Approach 1:
The patent applies preliminary action by using FIFO buffers to look ahead at future memory access patterns and predict which arrays will be needed soon. This allows the system to delay entering sleep mode until it is certain an array won't be accessed in the near future, avoiding unnecessary cycling while still capturing power savings from arrays that truly remain unused for extended periods
2Speed
If memory cell arrays are kept in standby mode to ensure availability, then access speed is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the memory array state configurable rather than fixed. The system dynamically adjusts the state of each array (sleep, standby, or active) based on real-time predictions of future access patterns, allowing optimal balance between power savings and access performance for each individual array
3Use of energy by moving object
If designers predict usage at design time to benefit from power savings, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies self-service by implementing an automated prediction mechanism that continuously monitors actual memory access patterns and updates its forecasts without human intervention. The FIFO buffers and control logic automatically adapt to changing usage patterns, eliminating the need for manual design-time prediction while maintaining effective power management
Data Source
AI summary
In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.