STT MRAM CSL Bias Scheme for Write Current and Oxide Stress

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Solution Overview

Problem

The Common Source Line (CSL) configuration in Spin Torque Transfer (STT) Magnetoresistive Random Access Memory (MRAM) limits writing methods, as all cells within a region share the same source line, restricting independent writing and affecting write current capability and standby power efficiency.

Innovation Solution

The proposed bias scheme involves applying a lower selected word line voltage (Vdd) for read and a higher voltage (Vpp) for write, with the source line and unselected bit lines driven to a non-zero voltage (Vsl0) during a write cycle, allowing the write current capability to be improved by increasing the selected write voltage beyond the maximum Gate to Source voltage (Vgs_max).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If a Common Source Line (CSL) configuration is used to reduce source line resistance and cell size, then the source line resistance decreases and cell area reduces, but the write current capability is limited due to shared source line constraints

Engineering Contradiction:

Improvesource line resistanceVSAvoidwrite current capability

Core Design Contradiction:

Length of stationary objectVSPower

Solution Approach 1:

The patent applies dynamic biasing by switching between two different word line voltage levels (Vdd for read, Vpp for write) based on the operation mode. During write operations, the higher Vpp voltage compensates for the shared source line constraint, enabling sufficient write current to flow through the common source line to all selected cells simultaneously, thus resolving the write current limitation while maintaining the CSL configuration benefits.

Inventive Principle:

Principle #15Dynamics

2Power

If a higher word line voltage is applied during write operations to improve write current capability, then the write current increases, but the gate oxide stress increases

Engineering Contradiction:

Improvewrite current capabilityVSAvoidgate oxide stress

Core Design Contradiction:

PowerVSObject-affected harmful factors

Solution Approach 1:

The patent changes the voltage parameter dynamically based on operation mode. By using Vpp (higher voltage) specifically during write operations and Vdd (lower voltage) during read operations, the system achieves sufficient write current when needed while minimizing gate oxide stress during normal operation. This parameter switching resolves the contradiction by applying high stress only when absolutely necessary for write operations.

Inventive Principle:

Principle #35Parameter changes

3Use of energy by stationary object

If the source line is held at zero voltage during standby to reduce power consumption, then standby current decreases, but the ability to write to multiple cells simultaneously is restricted

Engineering Contradiction:

Improvestandby powerVSAvoidmulti-cell write capability

Core Design Contradiction:

Use of energy by stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent dynamically adjusts the source line voltage based on the operation mode. During standby, the source line is held at zero voltage to minimize power consumption. During write operations, the source line voltage is dynamically switched to Vsl0 (non-zero), enabling simultaneous writing to multiple cells by providing the necessary voltage potential across the common source line. This dynamic switching resolves the contradiction between low standby power and multi-cell write capability.

Inventive Principle:

Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances write current capability while maintaining zero standby current in the array, even in the event of shorting defects, and reduces gate oxide stress, thereby improving the overall performance and reliability of the STT MRAM CSL array.

Implementation Method 1

Spin Torque Transfer (STT) Magnetoresistive Random Access Memory (MRAM) is an attractive emerging memory technology

Methodology Applied

Scientific EffectSpin Torque Transfer:

Implementation Method 2

A Bit Line (BL) is connected to the MTJ and runs perpendicular to the WL. A Source Line (SL) is connected to the FET

Methodology Applied

Scientific EffectField Effect:

Data Source

PatentUS9786343B1STT MRAM common source line array bias scheme

Publication Date: 2017.10.10 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Improved STT MRAM CSL array bias schemes are provided. In one aspect, a method for operating a CSL STT MRAM array includes: providing the STT MRAM array having a plurality of word lines perpendicular to both a plurality of bit lines and at least one source line; a plurality of memory cells including magnetic tunnel junctions in series with field effect transistors, wherein the field effect transistors are gated by the word lines, wherein the bit lines are connected to the magnetic tunnel junctions, and wherein the source line is connected to the field effect transistors; and applying a first word line voltage (Vdd) to a selected one of the word lines during a read, and a different second word line voltage (Vpp) to the selected word line during a write.