Data Storage Circuit Retains State During Precharge
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Solution Overview
Problem
Conventional sense amplifier latches face issues with high power consumption, topological restraints, and data loss when powered down, making them unsuitable for standard cell libraries and low power modes.
Innovation Solution
A data storage circuit with an input stage and output stage, utilizing dual data lines to control switching devices, allowing data retention during precharge phases without additional control signals, and incorporating a feedback loop with tristate inverters to maintain stored values, enabling low power operation and reduced area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sense amplifier latches are used with dual rail systems, then robust performance with high data slew is achieved, but power consumption increases due to discharge of one of the rails
Solution Approach 1:
The patent extracts the retention function from the conventional dual rail sense amplifier latch by using a separate output latch that retains data during precharge phases. This separates the data capture function (input latch) from the data retention function (output latch), allowing the input latch to operate efficiently while the output latch maintains data without requiring continuous dual rail operation, thereby reducing overall power consumption.
Solution Approach 2:
The data storage circuit is segmented into two distinct latches: an input latch for capturing data during evaluation phases and an output latch for retaining data during precharge phases. This segmentation allows each latch to be optimized for its specific function, with the output latch being able to retain data without the high power consumption associated with conventional dual rail systems.
2Productivity
If conventional sense amplifier latches are used, then data capture function is achieved, but topological restraints are significant
Solution Approach 1:
The output latch in the patent serves multiple functions: it retains data during precharge phases, outputs data during evaluation phases, and can be controlled by the dual data lines without requiring additional control signals. This multi-functionality reduces the need for separate control circuits and simplifies the overall topology, making the circuit more adaptable to standard cell library requirements.
3Reliability
If data retention capability is added to powered-down latches using associated balloon latch, then data retention in low power mode is achieved, but circuit area increases considerably
Solution Approach 1:
The patent merges the retention function into the existing output latch structure rather than adding a separate balloon latch. The output latch is configured to retain data during precharge phases using the dual data lines as control signals, eliminating the need for additional retention circuitry and reducing the overall circuit area while maintaining data retention capability in low power modes.
4Productivity
If conventional latches are used, then data storage function is achieved, but data is lost when powered down
Solution Approach 1:
The output latch is prepared in advance to retain data during precharge phases before the clock signal is turned off. By configuring the output latch to capture and hold data during the evaluation phase and maintain it during the subsequent precharge phase, the circuit ensures data is retained even when the input latch is powered down, preventing data loss.
Data Source
AI summary
A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.