Dynamic Redundancy Registers for STT-MRAM Write Error Management
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Solution Overview
Problem
Spin-transfer torque magnetic random access memory (STT-MRAM) devices suffer from high write error rates due to their inherently stochastic write mechanism, making them unreliable for data storage.
Innovation Solution
The implementation of dynamic redundancy registers in memory devices, allowing for simultaneous write and verify operations, and the use of pseudo-dual port memory banks to manage data storage and re-write attempts, thereby reducing write errors and improving memory reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If STT-MRAM devices use spin-polarized current to switch magnetization, then write speed can be achieved, but write error rate increases due to stochastic mechanism
Solution Approach 1:
The patent performs a verify read operation immediately after the write operation to check if the data was successfully written. If the verify fails, the system automatically performs a re-write operation. This preliminary verification and corrective action resolves the stochastic write failure issue while maintaining high write speed capability.
Solution Approach 2:
The patent implements a feedback mechanism where the verify read operation provides information about write success or failure. Based on this feedback, the control logic determines whether to perform a re-write operation. This closed-loop feedback system eliminates write errors while preserving the high-speed write capability of STT-MRAM.
2Reliability
If traditional separate verify method is used, then write errors can be detected, but additional time is required for separate verify operation
Solution Approach 1:
The patent merges the verify operation with the read operation by using the same read path and circuitry. The verify read shares the sense amplifiers, bit lines, and control logic with normal read operations. This consolidation eliminates the need for separate verify circuitry and reduces the time overhead, while still providing reliable write error detection.
3Reliability
If dynamic redundancy registers are implemented, then write error correction efficiency improves, but device complexity increases
Solution Approach 1:
The patent makes the read path and sense amplifiers serve dual purposes: normal read operations and verify operations. The same circuitry is used for both functions, controlled by different control signals. This multi-functionality approach provides error correction capability without adding dedicated verify circuitry, thus limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces write errors in STT-MRAM devices, enabling them to operate with high write error rates while maintaining data integrity and allowing for high write speed and low write voltage, thus enhancing bitcell endurance and error correction efficiency.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers.
Implementation Method 2
The second plate is typically referred to as the free layer and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to the reference layer.
Data Source
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AI summary
Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (e1 register) is couple to the memory bank. The e1 register may store data words that have failed verification or have not been verified. The e1 register may transfer data words to another dynamic redundancy register (e2 register). The e1 register may transfer data words that have failed to write to a memory bank after a predetermined number of re-write attempts. The e1 register may also transfer data words upon power down.