Segmented Pull-Down Transistors for Dual Port SRAM
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Solution Overview
Problem
Conventional dual port SRAM cells face issues with current crowding and junction leakage due to uneven device sizing and misalignment, leading to performance degradation and mismatch between pass-gate and pull-down transistors, which affects parallel operation efficiency.
Innovation Solution
A multi-port SRAM cell design with cross-coupled inverters and separate active regions for pull-down and pass-gate transistors, along with optimized metallization layers for balanced current distribution and reduced resistance, addressing current crowding and leakage issues while enabling parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If pull-down transistors are designed twice as wide as pass-gate transistors to sustain twice the drive current, then the drive current capability is improved, but device mismatching and current crowding occur due to uneven device sizing
Solution Approach 1:
The pull-down transistor is divided into two separate pull-down transistors instead of using one oversized transistor. This segmentation allows each pull-down transistor to have the same width as the pass-gate transistors, maintaining device matching while collectively providing the required drive current capability through parallel operation.
Solution Approach 2:
Instead of uniformly increasing the width of pull-down transistors across the entire device, the patent applies local quality by keeping individual pull-down transistor widths equal to pass-gate transistor widths, but increases the number of pull-down transistors locally to achieve the required total drive current while avoiding mismatching issues.
2Power
If L-shaped or T-shaped active regions are used to provide uneven device sizing, then the drive current requirement is met, but optical effects cause rounding at intersection regions leading to misalignment and performance degradation
Solution Approach 1:
The patent segments the pull-down function into separate transistors with simple rectangular active regions, eliminating the need for complex L-shaped or T-shaped active regions. This segmentation avoids optical rounding effects at intersections while maintaining the required drive current through parallel transistor operation.
Solution Approach 2:
Instead of using complex shaped active regions to achieve uneven sizing, the patent inverts the approach by using simple rectangular regions for all transistors and achieving the required current imbalance through the number of transistors rather than their individual sizes.
3Manufacturing precision
If gate poly of pass-gate transistor is misaligned upward, then the actual gate width becomes greater than desired, but mismatching occurs between pass-gate and pull-down transistors affecting SRAM cell performance
Solution Approach 1:
By segmenting the pull-down function into multiple transistors with widths equal to pass-gate transistors, the patent creates a configuration where mismatching has reduced impact. The parallel operation of multiple matched-sized transistors provides redundancy and stability against individual transistor variations.
4Power
If currents are concentrated at the intersection region, then current crowding occurs, but junction leakage increases due to uneven current distribution
Solution Approach 1:
The patent segments the current path through multiple parallel transistor channels instead of concentrating current through a single oversized transistor or complex intersection region. This segmentation distributes current evenly across multiple simple rectangular active regions, eliminating current crowding and reducing junction leakage.
Data Source
AI summary
A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor, wherein the pull down transistors of the first inverter are formed in a first active region, the pull down transistors of the second inverter are formed in a second active region, the pass gate transistors coupled to the data storage node are formed in a third active region and the pass gate transistors coupled to the data bar storage node are formed in a fourth active region.