Memory Write Multiplexer Segmentation for Fan-In Reduction
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Solution Overview
Problem
Existing memory systems with multiple write ports face operational difficulties due to fan-in issues, requiring redesign of storage elements and multiplexers, which complicates reliable memory operation.
Innovation Solution
A memory design featuring regular arrays of storage elements and write multiplexers, where the multiplexers are arranged outside the storage elements, allowing for flexible selection of write ports and addressing fan-in issues through a common word line signal and domino logic multiplexers, enabling efficient data transfer and reuse of storage elements with different multiplexer configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of write ports is varied in memory design, then the memory can support different write port configurations, but the elements within the array need to be redesigned causing fan-in issues that impact reliable operation
Solution Approach 1:
The memory array is segmented into multiple banks, each bank having its own dedicated write multiplexer. This segmentation allows each multiplexer to handle a manageable number of inputs, avoiding fan-in issues while supporting multiple write ports across the entire memory structure. Each bank operates independently with controlled signal routing.
Solution Approach 2:
The patent introduces a bank dimension to the memory architecture, organizing storage elements and multiplexers in a two-dimensional hierarchy (banks × columns). This dimensional organization allows multiple write ports to be supported by distributing them across different banks, reducing the fan-in to individual multiplexers while maintaining overall system versatility.
2Adaptability or versatility
If elements within the array are redesigned to support varied write ports, then different write port configurations are supported, but the complexity of the memory design increases
Solution Approach 1:
The memory banks are designed with universal interfaces that can accommodate multiple write port configurations. Each bank uses standardized multiplexer structures that can be configured for different numbers of write ports through control logic rather than structural redesign, reducing overall design complexity while maintaining versatility.
Solution Approach 2:
The memory architecture uses dynamic configuration through control signals and multiplexer selection logic rather than static structural changes. This allows the same physical structure to support different write port configurations by dynamically routing signals, reducing design complexity compared to static redesign approaches.
3Adaptability or versatility
If fan-in to each storage element is increased to support multiple write ports, then more write ports are supported, but the reliable operation of the memory is impacted
Solution Approach 1:
By segmenting the memory into banks with dedicated multiplexers, the fan-in to each storage element is limited to a manageable number of inputs. Each multiplexer selects from a small set of bit lines within its bank, preventing excessive fan-in while supporting multiple write ports across the entire memory through the bank structure.
Data Source
AI summary
A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.