Computational Memory Array with Distributed ALU Logic
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Solution Overview
Problem
Conventional microprocessor designs require a physical arithmetic logic unit (ALU) close to memory to enhance computational power, increasing die area and cost, and existing attempts to integrate computational capability within memory arrays face high overhead and limitations in performing operations on multiple operands simultaneously.
Innovation Solution
A memory array design with a distributed ALU capability, utilizing a modified memory cell structure and read word lines to perform bitwise logical operations on multiple operands concurrently without a discrete ALU, allowing for simultaneous read and computation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a physical ALU circuit is incorporated into the memory structure to improve computational power, then computational capability is enhanced, but die area and manufacturing cost increase
Solution Approach 1:
The memory array is designed to perform multiple functions: it can operate as a conventional memory array for data storage and retrieval, or it can perform bitwise logical operations (AND, OR, XOR, NOT) by selectively activating word lines. This multi-functionality eliminates the need for a separate physical ALU circuit, thereby avoiding increased die area while maintaining computational capability.
Solution Approach 2:
The computational functions are merged with the memory array structure itself. By utilizing the existing memory cells and word lines, the patent combines storage and computation functions into a single structure, avoiding the need for separate ALU circuits and reducing overall die area.
2Speed
If a bit-wise ALU is attached to sense amplifiers in memory arrays to increase computational speed, then processing speed improves, but overhead becomes high for small memories
Solution Approach 1:
The computational logic is merged directly into the memory array structure by utilizing the existing sense amplifiers and word line control mechanisms. This integration eliminates the need for separate ALU circuits and reduces overhead, particularly benefiting small memory arrays where the overhead of dedicated ALU circuits would be significant.
Solution Approach 2:
The memory array structure is designed to serve dual purposes: conventional memory operations and bitwise logical computations. By controlling which word lines are activated, the same hardware structure can perform either memory access or logical operations, eliminating the need for dedicated computational hardware and reducing overall device complexity.
3Measurement precision
If operands are read out one at a time to be computed in an attached ALU, then computational accuracy is maintained, but processing time increases
Solution Approach 1:
The memory array enables continuous computation by performing bitwise logical operations directly on multiple operands simultaneously while they remain stored in the array. By selectively activating word lines corresponding to different operands, the system can compute results from multiple operands in parallel without the need to sequentially read them out, thereby maintaining computational accuracy while significantly reducing processing time.
Solution Approach 2:
The patent transitions from sequential processing (reading operands one at a time) to parallel processing by utilizing the spatial dimension of the memory array. Multiple operands can be selected simultaneously through word line activation, enabling parallel computation across multiple data words and dramatically reducing processing time while maintaining accuracy.
Data Source
AI summary
A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.