Shared Electrode MRAM Architecture for Contact Resistance
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Solution Overview
Problem
Existing MRAM technologies face challenges in reducing contact resistance to MTJ stacks and preventing damage during the formation of overlying metallization layers.
Innovation Solution
The implementation of shared electrodes for MTJ stacks, which reduces contact resistance, and the formation of dielectric protective structures around MRAM cells to prevent etching during subsequent processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate electrodes are used for each MTJ stack, then individual connection is achieved, but contact resistance is high
Solution Approach 1:
Multiple separate electrodes for individual MTJ stacks are merged into a single shared electrode that serves multiple MTJ stacks simultaneously. This consolidation reduces the total number of electrodes and interconnects, thereby reducing contact resistance while maintaining individual access to each MTJ stack through selective switching mechanisms.
Solution Approach 2:
The shared electrode structure is designed to perform multiple functions: it serves as a common electrical connection for multiple MTJ stacks, acts as a reference potential, and enables selective addressing of individual stacks through crossbar switching. This multi-functionality reduces the overall complexity of the electrode system while improving reliability.
2Manufacturing precision
If etching is used to form overlying metallization layers, then precise patterning is achieved, but damage to MRAM cells occurs
Solution Approach 1:
A dielectric protective structure is introduced as an intermediary layer between the MRAM cells and the etching process. This protective structure acts as a barrier that prevents direct contact between the etchant and the sensitive MRAM cell components, allowing precise patterning to proceed while protecting the cells from damage.
Solution Approach 2:
The dielectric protective structure is formed in advance, before the etching of overlying metallization layers. This preliminary protective action ensures that when subsequent etching steps are performed, the MRAM cells are already shielded, preventing damage while maintaining manufacturing precision.
3Ease of operation
If multiple separate electrodes are used for each MTJ stack, then individual control is maintained, but device complexity increases
Solution Approach 1:
Multiple individual electrodes are merged into shared electrodes that serve multiple MTJ stacks. Individual control is maintained through selective switching mechanisms in the crossbar architecture, which enable specific MTJ stacks to be accessed and controlled independently despite sharing common electrodes, thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and minimizes damage to MRAM cells during processing, enhancing the reliability and yield of MRAM device manufacturing.
Implementation Method 1
One type of semiconductor memory is magnetoresistive random access memory (MRAM), which involves spin electronics that combines semiconductor technology and magnetic materials and devices. The spins of electrons, through their magnetic moments, are used to indicate bit values.
Implementation Method 2
A MRAM cell typically includes a magnetic tunnel junction (MTJ) stack, which includes two ferromagnets separated by a thin insulator
Data Source
AI summary
In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.