SRAM Memory Bank Segmentation for Parallel Data Access
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Solution Overview
Problem
Current SRAM memory circuits face inefficiencies in data access due to sequential activation of word lines and bit lines, leading to processor idle time and limited memory transfer rates, which hinder computing system throughput.
Innovation Solution
The SRAM circuit enables simultaneous independent activation of word lines and bit lines, allowing concurrent access to multiple rows and columns, with flexible data access capabilities that support segment-free operations, reducing processor idle time and improving memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential activation of word lines and bit lines is used in SRAM memory circuits, then the circuit structure remains simple, but data access speed is limited and processor idle time increases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank having independent word lines and bit lines. This segmentation allows simultaneous access to multiple banks without interference, enabling parallel data operations and reducing processor idle time while maintaining simple circuit structures within each bank.
Solution Approach 2:
The patent introduces a bank selection dimension in addition to the traditional row-column addressing. By adding this dimensional layer, the system can simultaneously activate word lines across multiple banks while selecting specific bit lines, achieving parallel access that increases data transfer rates without complicating the fundamental circuit design.
2Adaptability or versatility
If multiple word lines are activated simultaneously to access memory cells in different rows, then data access flexibility is improved, but access cycles increase due to column access requirements
Solution Approach 1:
By dividing the memory into independent banks with separate column structures, the patent allows simultaneous activation of multiple word lines across different banks without the column access bottleneck. Each bank can independently complete its read/write operation, maintaining high productivity while providing flexible multi-row access capability.
3Productivity
If processor speed is increased to improve computing system throughput, then processing capability is enhanced, but the mismatch with memory transfer rates causes increased processor idle time
Solution Approach 1:
The patent enables preliminary data preparation by allowing multiple banks to be pre-loaded or pre-accessed in parallel. This preliminary action ensures that data is ready in the memory system before the processor needs it, eliminating processor idle time and maintaining high computing system throughput without requiring faster memory transfer rates.
Data Source
AI summary
A static random access memory (SRAM) circuit can group the column bit lines in a memory array into subsets of bit lines, and a y-address signal input is provided for each subset of bit lines. Additionally or alternatively, each row in the array of memory cells is operably connected to multiple word lines.